zl30116 Zarlink Semiconductor, zl30116 Datasheet - Page 17

• Manufacturer Part Number: zl30116
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference
clock cycles within the frame pulse period.
1.5
The ZL30116 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n,
diff1_p/n), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks, and four programmable LVCMOS
(p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH
frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also
available.
The feedback clock (fb_clk) of DPLL1 is available as an output clock. Its output frequency is always equal to
DPLL1’s selected input frequency.
The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and
the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1
or DPLL2. This allows the ZL30116 to have two independent timing paths.
Output Clocks and Frame Pulses
DPLL2
DPLL1
Figure 6 - Output Clock Configuration
Zarlink Semiconductor Inc.
ZL30116
17
SONET/SDH
Synthesizer
Synthesizer
Synthesizer
Feedback
APLL
P0
P1
p0_clk0
p0_fp0
p0_clk1
p0_fp1
p1_clk0
p1_clk1
sdh_clk0
sdh_fp0
sdh_clk1
sdh_fp1
diff0
diff1
fb_clk
Data Sheet