zl30116 Zarlink Semiconductor, zl30116 Datasheet - Page 23

• Manufacturer Part Number: zl30116
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
1C
1D
0F
1A
1B
1E
10
11
12
13
14
15
16
17
18
19
ref_mon_fail_mask_3
detected_ref_0
detected_ref_1
detected_ref_2
detected_ref_3
detected_sync_0
detected_sync_1
oor_ctrl_0
oor_ctrl_1
oor_ctrl_2
oor_ctrl_3
gst_mask_0
gst_mask_1
gst_qualif_time
dpll1_ctrl_0
dpll1_ctrl_1
Register
Name
Table 5 - Register Map (continued)
Description
Description
Register
Register
Reset
Value
(Hex)
See
See
EE
FF
FF
FF
FF
FF
0E
FF
FF
1A
33
33
33
33
Zarlink Semiconductor Inc.
Reference Monitor Setup
ZL30116
DPLL1 Control
Control register to mask each failure indicator
for ref6 and ref7
Ref0 and ref1 auto-detected frequency value
status register
Ref2 and ref3 auto-detected frequency value
status register
Ref4 and ref5 auto-detected frequency value
status register
Ref6 and ref7 auto-detected frequency value
status register
Sync0 and sync1 auto-detected frequency
value and sync failure status register
Sync2 auto-detected frequency value and sync
valid status register
Control register for the ref0 and ref1 out of
range limit
Control register for the ref2 and ref3 out of
range limit
Control register for the ref4 and ref5 out of
range limit
Control register for the ref6 and ref7 out of
range limit
Control register to mask the inputs to the guard
soak timer for ref0 to ref3
Control register to mask the inputs to the guard
soak timer for ref4 to ref7
Control register for the guard_soak_timer
qualification time and disqualification time for
the references
Control register for the DPLL1 filter control;
phase slope limit, bandwidth and hitless
switching
Holdover update time, filter_out_en,
freq_offset_en, revert enable
23
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R