zl30116 Zarlink Semiconductor, zl30116 Datasheet - Page 7

• Manufacturer Part Number: zl30116
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
Input Reference
Output Clocks and Frame Pulses
Pin #
D10
G10
E10
F10
C1
B2
A3
C3
B3
B4
C4
A4
B1
A1
A2
C5
B5
K9
K7
ext_fb_clk
ext_fb_fp
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
p0_clk0
p0_clk1
Name
sync0
sync1
sync2
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
Type
I/O
O
O
O
O
O
O
I
I
I
I
d
d
d
d
Input References (LVCMOS, Schmitt Trigger). These are input references
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can be automatically or manually selected using software
registers. These pins are internally pulled down to Vss.
Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).
These are the frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled down to V
External DPLL Feedback Clock (LVCMOS, Schmitt Trigger). External
feedback clock input. This allows DPLL1 to adjust for PCB trace propagation
delays. This pin is internally pulled down to Vss. Leave open when not is use.
External DPLL Feedback Frame Pulse (LVCMOS, Schmitt Trigger). External
feedback frame pulse input. This allows DPLL1 to adjust for PCB trace
propagation delays. This pin is internally pulled down to Vss. Leave open when
not is use.
SONET/SDH Output Clock 0 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 77.76 MHz.
SONET/SDH Output Clock 1 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 19.44 MHz.
SONET/SDH Output Frame Pulse 0 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 8 kHz.
SONET/SDH Output Frame Pulse 1 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 2 kHz.
Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 8.192 MHz.
Zarlink Semiconductor Inc.
ZL30116
7
Description
ss.
Data Sheet