zl30120 Zarlink Semiconductor, zl30120 Datasheet
zl30120
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zl30120 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. Multi-Rate Line Card Synchronizer an email to ZL30120GGG ZL30120GGG2 100 Pin CABGA** **Pb Free Tin/Silver/Copper • Provides two DPLLs which have independent modes of operation (locked, free-run, holdover) and optional hitless reference switching. • ...
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... Applications TM • AMCs for AdvancedTCA and MicroTCA Systems • Synchronous Ethernet • Multi-Service Edge Switches or Routers • DSLAM Line Cards • WAN Line Cards • RNC/Mobile Switching Center Line Cards • ADM Line Cards ZL30120 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ZL30120 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ZL30120 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ZL30120 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...
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... The default frequency for this frame pulse output is 8 kHz. J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. ZL30120 Description ss. 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Serial Interface Input (LVCMOS). Serial interface data input pin Serial Interface Output (LVCMOS). Serial interface data output pin. E3 cs_b I Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This u pin is internally pulled up to Vdd. ZL30120 Description 7 Zarlink Semiconductor Inc. Data Sheet ...
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... K5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. Miscellaneous Connection. Leave unconnected. A10 B5 B9 B10 ZL30120 Description 8 Zarlink Semiconductor Inc. Data Sheet . If this pin is not used DD ...
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... Positive Analog Supply Voltage. +1.8V CORE Ground. 0 Volts ZL30120 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet ...
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... I/O Pin # Name Type Analog Ground. 0 Volts Input I - Input, Internally pulled down Input, Internally pulled Output A - Analog P - Power G - Ground ZL30120 Description 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. ...
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... The input references are continuously monitored for frequency accuracy and phase regularity least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30120 will enter in the Normal (locked) mode. Normal (locked) ...
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... DPLL will align the output frame pulses to the output clock edge that is aligned to the input frame pulse. ZL30120 DPLL2 ref7:0 DPLL1 Figure 3 - Reference and Sync Inputs input is selected with its corresponding ref n ref n ...
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... Single Cycle Monitor (SCM) The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure (scm_fail) is declared. ZL30120 2 kHz 8 kHz 64 kHz 1 ...
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... Output Clocks and Frame Pulses The ZL30120 offers a wide variety of outputs including two low jitter LVCMOS (apll_clk0, apll_clk1) output clocks and four programmable LVCMOS (p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS frame pulse outputs (apll_fp0, apll_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also available ...
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... The output clocks and frame pulses derived from the low jitter APLL are always synchronous with DPLL1, and the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1 or DPLL2. This allows the ZL30120 to have two independent timing paths. DPLL2 DPLL1 The supported frequencies for the output clocks and frame pulses are shown in Table 4 ...
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... Configurable Input-to-Output and Output-to-Output Delays The ZL30120 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. All of the output synthesizers (APLL, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag the selected input reference clock using the DPLL1 Fine Delay ...
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... Software Configuration The ZL30120 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor can operate in a manual mode where the system processor controls most of the operation of the device ...
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... ZL30120 Reset Value Description (Hex) FF Control register to mask each failure indicator for ref6 and ref7 Reference Monitor Setup FF Ref0 and ref1 auto-detected frequency value status register FF Ref2 and ref3 auto-detected frequency value status register ...
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... ZL30120 Reset Value Description (Hex) See Control register for the DPLL1 mode of operation Register Description 00 DPLL1 reference selection or reference selection status 3C Control register to mask each failure indicator (SCM, CFM, PFM and GST) used for automatic ...
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... ZL30120 Reset Value Description (Hex) 00 Control register for the ref0 to ref7 enable revertive signals 10 Control register for the ref0 and ref1 priority values 32 Control register for the ref2 and ref3 priority values 54 Control register for the ref4 and re5 priority ...
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... ZL30120 Reset Value Description (Hex) 00 Bits [21:16] of the programmable frame pulse phase offset in multiples of 8 kHz cycles 05 Control register to select p0_fp1 frame pulse frequency 11 Control register to select fp1 type 00 Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/262 ...
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... ZL30120 Reset Value Description (Hex) 00 Control register for the apll_clk1 phase position coarse tuning 00 Control register for the output/output phase alignment fine tuning for apll path 05 Control register to select the apll_fp0 frame pulse frequency ...
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... ZL30120 Reset Value Description (Hex) 00 Control register for the [7:0] bits of the custom configuration A. This is the N integer for the N*8kHz reference monitoring. 00 Control register for the [13:8] bits of the custom configuration A. This is the N integer for the N*8kHz reference monitoring. ...
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... Reserved 7F 3.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. This datasheet provides a summary of the high level features of the ZL30120. Refer to the ZL30120 Design Manual for a more complete description. ZL30120 Reset Value Description ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...