zl30120 Zarlink Semiconductor, zl30120 Datasheet - Page 16

• Manufacturer Part Number: zl30120
• Description: Sonet/sdh/ethernet Multi-rate Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

The output clocks and frame pulses derived from the low jitter APLL are always synchronous with DPLL1, and the
clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1 or
DPLL2. This allows the ZL30120 to have two independent timing paths.
The supported frequencies for the output clocks and frame pulses are shown in Table 4.
1. The apll_clk
2. apll_fp
(LVCMOS)
12.96 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
apll_clk0,
6.48 MHz
9.72 MHz
apll_clk1
25 MHz
50 MHz
x
frequencies are available only when the low jitter apll is generating SONET/SDH frequencies
DPLL2
DPLL1
1
x
outputs can generate either SONET/SDH or Ethernet frequencies (25 MHz, 50 MHz).
Table 4 - Output Clock and Frame Pulse Frequencies
p0_clk0, p1_clk0
N * 8 kHz (up to
(LVCMOS)
Figure 6 - Output Clock Configuration
100 MHz)
2 kHz
Zarlink Semiconductor Inc.
ZL30120
16
p
p0_clk1, p1_clk1
x
_clk1 =
Synthesizer
Synthesizer
Synthesizer
(LVCMOS)
Low Jitter
Feedback
APLL
P0
P1
p
2
x
_clk0
M
(48x 125 2s frames)
apll_fp0, apll_fp1,
p0_clk0
p0_fp0
p0_clk1
p0_fp1
p1_clk0
p1_clk1
apll_clk0
apll_fp0
apll_clk1
apll_fp1
fb_clk
p0_fp0, p0_fp1
(LVCMOS)
166.67 Hz
400 Hz
32 kHz
64 kHz
1 kHz
2 kHz
4 kHz
8 kHz
2
Data Sheet