zl30120 Zarlink Semiconductor, zl30120 Datasheet - Page 8

• Manufacturer Part Number: zl30120
• Description: Sonet/sdh/ethernet Multi-rate Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

APLL Loop Filter
JTAG and Test
Master Clock
Miscellaneous
Pin #
A10
B10
G2
C6
H4
C5
D1
D3
G3
A6
B6
K2
K3
K4
K5
A9
B5
B9
J4
J3
filter_ref0
filter_ref1
apll_filter
Name
trst_b
int_b
osco
osci
tms
NC
tdo
tck
tdi
Type
I/O
O
O
I
I
I
O
A
A
A
I
I
u
u
u
Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled up to VDD.
External Analog PLL Loop Filter terminal.
Analog PLL External Loop Filter Reference.
Analog PLL External Loop Filter Reference.
Test Serial Data Out (Output). JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
then it should be left unconnected.
Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of
the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
No Connection. Leave unconnected.
Zarlink Semiconductor Inc.
ZL30120
8
Description
DD
. If this pin is not used
Data Sheet