mt90863al1 Zarlink Semiconductor, mt90863al1 Datasheet - Page 14

• Manufacturer Part Number: mt90863al1
• Description: 2,048 X 512 Channel 3.3 V Rate Conversion Digital Switch Rcdx , H.100 Compatible
• Manufacturer: Zarlink Semiconductor

3.5
The MT90863 provides the frame evaluation inputs, FEi0 to FEi23, to determine different data input delays with
respect to the frame pulse F0i. By using the frame evaluation input select bits (FE0 to FE4) of the frame alignment
register (FAR), users can select one of the twenty-four frame evaluation inputs for the frame alignment
measurement.
A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the
evaluation starts when the SFE bit in the Internal Mode Selection (IMS) register is changed from low to high. One
frame later, the complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to
signal that a valid offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be
set to zero before a new measurement cycle is started.
BMS2
0
0
0
0
1
1
1
DMS Register Bits
Serial Input Frame Alignment Evaluation
Timing Signals
F0o Width
F0i Width
C4i/C8i
C16i
BMS1
C4o
0
0
1
1
0
0
1
Table 1 - Timing Signals Requirements for Various Operation Modes
BMS0
0
1
0
1
0
1
0
Table 2 - Mode Selection for Backplane interface
2 Mb/s, ST-BUS Mode
4 Mb/s, ST-BUS Mode
8 Mb/s, ST-BUS Mode
2 Mb/s, CT Bus Mode
4 Mb/s, CT Bus Mode
8 Mb/s, CT Bus Mode
ST-BUS Mode
HMVIP Mode
Not Required
Modes
61 ns
Zarlink Semiconductor Inc.
MT90863
14
Backplane Interface
CT Bus Mode
16.384 MHz
8.192 MHz
4.096 MHz
STio16 - 31
STio16 - 31
STio16 - 23
STio24 - 31
STio0 - 31
STio0 - 31
STio0 - 31
STio0 - 31
STio0 - 15
STio0 - 15
STio0 - 15
122 ns
244 ns
HMVIP Mode
Not available
Not available
Not available
2.048 Mb/s
2.048 Mb/s
4.096 Mb/s
4.096 Mb/s
8.192 Mb/s
8.192 Mb/s
2.048 Mb/s
8.192 Mb/s
4.096 MHz
Data Rate
244 ns
Data Sheet