mt90863al1 Zarlink Semiconductor, mt90863al1 Datasheet - Page 29

• Manufacturer Part Number: mt90863al1
• Description: 2,048 X 512 Channel 3.3 V Rate Conversion Digital Switch Rcdx , H.100 Compatible
• Manufacturer: Zarlink Semiconductor

15 - 0
11 - 5
4 - 0
Bit
Bit
15
14
13
12
WR15
Read/Write Address:
Reset value:
Read/Write Address:
Reset value:
15
15
0
WR14
CDA
14
14
WR15 - WR0
CA6 - CA0
SA4 - SA0
unused
Name
Name
WR13
CDA
RS
WS
13
RS
13
WR12
WS
12
12
Table 13 - Address Buffer (ABR) Register Bits
WR11
CA6
11
11
Reserved
Complete Data Access. This bit is read only. This bit changes from 0 to 1
when data transfer is completed between memory and the data read register or
data write register. When the RS or WS bit in this register is changed from 1 to
0, this bit is reset to zero.
Read Select. A zero to one transition of this bit initiates the data transfer from
memory to the data read register. This bit is reset to zero when the CDA bit
changes from 0 to 1.
Write Select. A zero to one transition of this bit initiates the data transfer from
the data write register to memory. This bit is reset to zero when the CDA bit
changes from 0 to 1.
Channel Address Bits. These bits perform the same function as the external
address bits when used to access various memory locations. The number
(expressed in binary notation) on these bits refers to the input or output data
stream channel that corresponds to the subsection of memory.
Stream Address Bits. These bits perform the same function as the STA bits in
the control register. The number (in binary notation) on these bits refers to the
input or output data stream which corresponds to the subsection of memory.
Write Data Bits. Data to be transferred to the internal memory locations.
0C
0000
0D
0000
Table 14 - Data Write (DWR) Register Bits
H
H
for ABR register,
for DWR register,
WR10
H
H
CA5
10
10
CA4
WR9
Zarlink Semiconductor Inc.
9
9
MT90863
CA3
WR8
8
8
29
CA2
WR7
7
7
CA1
WR6
6
6
Description
Description
CA0
WR5
5
5
SA4
WR4
4
4
SA3
WR3
3
3
SA2
WR2
2
2
SA1
WR1
1
1
Data Sheet
SA0
WR0
0
0