mt90863al1 Zarlink Semiconductor, mt90863al1 Datasheet - Page 16

• Manufacturer Part Number: mt90863al1
• Description: 2,048 X 512 Channel 3.3 V Rate Conversion Digital Switch Rcdx , H.100 Compatible
• Manufacturer: Zarlink Semiconductor

4.1
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams.
4.2
In this mode a multiple data memory buffer is used to maintain frame integrity in all switching configurations.
5.0
The MT90863 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is
compatible with Motorola non-multiplexed buses. The required microprocessor signals are the 16-bit data bus (D0-
D15), 8-bit address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 16 - Figure 16 for Motorola
non-multiplexed bus timing.
The MT90863 microprocessor port provides access to the internal registers, connection and data memories. All
locations provide read/write access except for the Data Memory and the Data Read Register which are read only.
5.1
The address bus on the microprocessor interface selects the internal registers and memories of the MT90863. If
the A7 address input is low, then the registers are addressed by A6 to A0 as shown in Table 4.
If the A7 is high, the remaining address input lines are used to select the serial input or output data streams
corresponding to the subsection of memory positions. For data memory reads, the serial inputs are selected. For
connection memory writes, the serial outputs are selected.
The control, device mode selection and internal mode selection registers control all the major functions of the
device. The device mode selection register and internal mode selection register should be programmed
immediately after system power-up to establish the desired switching configuration as explained in the Frame
Alignment Timing and Switching Configurations sections.
The control register is used to control the switching operations in the MT90863. It selects the internal memory
locations that specify the input and output channels selected for switching.
Control register data consists of: the memory block programming bit (MBP): the memory select bits (MS0-2); and,
the stream address bits (STA0-4). The memory block programming bit allows users to program the entire
connection memory block, (see Memory Block Programming section). The memory select bits control the selection
of the connection memory or the data memory. The stream address bits define an internal memory subsections
corresponding to serial input or serial output streams.
Variable Delay Mode (LV/C or BV/C bit = 0)
Constant Delay Mode (LV/C bit or BV/C= 1)
Memory Mapping
Microprocessor Interface
Zarlink Semiconductor Inc.
MT90863
16
Data Sheet