mt9085bpr1 Zarlink Semiconductor, mt9085bpr1 Datasheet - Page 11

• Manufacturer Part Number: mt9085bpr1
• Description: Pac - Parallel Access Circuit
• Manufacturer: Zarlink Semiconductor

Applications
1024 Channel Digital Time-Space Switch
A 1024 channel serial time-space digital switch design is illustrated in Figure 9.
The main switching function is accomplished using two MT9080s (SMXs). One SMX is operated in the Data
Memory mode and the second serves as the Connection Memory. Refer to the SMX data sheet for more
information on this configuration. The serial to parallel conversion function is provided by a PAC configured for
2.048 Mbit/s operation (2/4S = 0). The MCB input in this PAC is tied high to ensure data output by the PAC meets
SMX input setup and hold requirement. PAC #2 performs the parallel to serial function; MCA is set high. The MCB
input in this device is set low to allow data to be clocked in with the falling edge of C16.
The main timing source generates a 16.384 MHz clock phase locked to a 4.096 MHz clock. The framing signal
input to PAC#1 at F0i should meet the requirements specified in Figure 13 of this data sheet. In some applications
where a master 16.384 MHz oscillator is used for system timing, the C4i and F0i clocks could be derived directly
from it. In applications where a 4.096 MHz clock signal is available, the 16.384 MHz clock can be generated using
a phase-lock loop.
S0
S31
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OE CKD MCA MCB
S0
S31
2/4S
F0i
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Source
Timing
C4i C16i
PAC#1
S/P
Figure 9 - 1024 Channel Switch Matrix Using the PAC and SMX
P0-P7
C16
DFPo
CFPo
+5
C4
F0
C16
8
C16
+5
CK
FP
D12
Zarlink Semiconductor Inc.
D0-D7i
CK
FP
Mz
R/W
ODE
MT9085B
MPU Interface
CONNECTION
SMX #2
CM - 1
MEMORY
DM - 1/2
SMX #1
MEMORY
D0-D9
A0-A9 ME
DATA
11
10
D0-D7o
ODE
D11
D10
Mx
My
Mz
DS
Mx
My
CS
8
+5
+5
NOTE: Connect all inputs not shown to V
From Timing Source
F0 C4 C16
F0i C4i C16i
OE CKD MCA MCB
P0-P7
PAC#2
P/S
+5
2/4S
S31
S0
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Data Sheet
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S0
S31
SS