mt9085bpr1 Zarlink Semiconductor, mt9085bpr1 Datasheet - Page 5

• Manufacturer Part Number: mt9085bpr1
• Description: Pac - Parallel Access Circuit
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
60-67
Pin #
C16i
C4o
C2o
F0o
Serial I/O
2 Mbit/s
Serial I/O
4 Mbit/S
C4
F0
S0-S31
2/4S = 0
S0-S15
2/4S = 1
68
Name
P0-P7
V
DD
Ch. 31 Bit 1
Parallel Input/Output Data Bus. This 8 bit data bus is an output in serial to parallel mode (MCA=0),
and an input in parallel to serial mode (MCA=1). Data is clocked in and out of the port by the C16 clock.
The state of the CKD pin determines the relative phase of the critical clock edges with respect to the
frame pulse. All inputs/outputs have internal pullups. Refer to Figures 6 and 7 for functional timing
information.
Supply. +5 V
Ch. 63 Bit 2
0
0
1
Figure 4 - Channel and Frame Alignment (CKD = 0)
Figure 3 - Serial Input/Output Functional Timing
Ch. 63 Bit 1
2
Ch. 31 Bit 0
1
Frame Boundary Established by F0i
Zarlink Semiconductor Inc.
3
Ch. 63 Bit 0
MT9085B
512 C4 Cycles
5
Description
Ch. 0 Bit 7
Ch. 0 Bit 7
Ch. 0 Bit 6
31
63
Ch. 0 Bit 5
0
Ch. 0 Bit 6
0
Data Sheet