mt9085bpr1 Zarlink Semiconductor, mt9085bpr1 Datasheet - Page 9

• Manufacturer Part Number: mt9085bpr1
• Description: Pac - Parallel Access Circuit
• Manufacturer: Zarlink Semiconductor

Data on the eight bit parallel bus (P0-P7) is clocked into the device with the C16i clock. It is clocked out on the serial
streams at either 2.048 Mbit/s (2/4S =0) or at 4.096 Mbit/s (2/4S=1). See Figures 16, 17 and 19 for timing
information.
Contiguous channels clocked into the device are output on the serial streams in an interleaved manner on each of
the serial outputs. For example when the device is configured for 2.048 Mbit/s data rate, the first 32 parallel
channels clocked into the device will be clocked out during channel 0 on serial streams 0 to 31. Channel 1 on serial
streams 0 to 31 will contain data from the next 32 timeslots. On any single serial stream, consecutive output
channels are sourced from every 32nd parallel input channel (see Figures 6 and 8). When the device is configured
for 4.096 Mbit/s serial output operation, contiguous channels on the serial streams are sourced from every 16th
parallel input channel.
Data on the eight bit parallel bus is clocked into the device with the C16 clock. The level asserted on the MCB input
specifies whether the data is clocked into the device on the falling edge or the rising edge of C16. The relative
phase of the critical edge with respect to the system frame boundary is defined by the level asserted on the CKD
pin as illustrated in Figure 16. The flexibility in input timing permits the PAC to be easily interfaced to the SMX in
1024 and 2048 switching applications. Refer to the applications section of this data sheet for more details.
The delay through the PAC is approximately one ST-BUS channel time when the device is operated in 2.048 Mbit/s
mode, i.e., any specific channel clocked into the device will be clocked out one ST-BUS channel later. In the 4.096
Mbit/s mode, the delay is equal to eight C4 clock cycles.
Serial output channel timeslots can be tri-stated by setting OE high during a specific parallel channel timeslot. The timing
for OE is described in Figures 6 and 21. Note that the level asserted on MCB affects the operation of OE.
0 1 2 3 4 5 6 7
CH. 2
TS64
TS65
TS95
•
•
•
•
•
•
•
•
0 1 2 3 4 5 6 7
CH. 1
TS32
TS33
TS63
•
•
•
•
0 1 2 3 4 5 6 7
TS31
CH. 0
TS0
TS1
•
•
•
•
Figure 8 - PAC Operation at 2.048 Mbit/s
Parallel to Serial Conversion
Serial to Parallel Conversion
Bit #
Zarlink Semiconductor Inc.
S0
S1
S31
•
•
•
•
MT9085B
PAC
9
P0
P1
P2
P3
P4
P5
P6
P7
TS
0
0
1
2
3
4
5
6
7
TS
1
0
1
2
3
4
5
6
7
TS
31
0
1
2
3
4
5
6
7
TS
32
0
1
2
3
4
5
6
7
TS
33
0
1
2
3
4
5
6
7
TS
63
0
1
2
3
4
5
6
7
TS
64
0
1
2
3
4
5
6
7
Data Sheet