mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 15

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

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Capable of operating in UTOPIA Level 1 mode (8-bit bus running at up to 25 MHz), for connection to older
devices
Supports up to 256 bidirectional VCCs (Structured Nx64 mode)
VPI/VCI Match and Match Enable filter prevents excessive look-up table accesses to external memory
Cell reception based on look-up table allows flexible VCC assignment for CBR VCCs (allows non-
contiguous VCC assignment)
Supports AAL1 Segmentation and Reassembly for Structured and Unstructured CES as specified in af-vtoa-
0078.000
Supports non-multiframe or multiframe circuit emulation, using AAL1 structure formats as described in af-
vtoa-0078.000: Nx64 Basic Service (single frame structure) or DS1 or E1 Nx64 Service with CAS
(multiframe structure)
Supports transmission and reception of up to 128 TDM channels per VCC in accordance with af-vtoa-
0089.001 (ATM Trunking using AAL1 for Narrowband Services)
Supports Unstructured CES and Structured CES simultaneously on different ports
Supports 8 bidirectional VCCs, carrying 1.544 Mbps or 2.048 Mbps, in Unstructured CES mode
Supports up to 256 bidirectional VCCs, carrying from 1 to 128 DS0 (64 kbps) TDM channels, in Structured
CES mode (up to 256 DS0 channels total)
UDT reassembly works with 8 per-port timing engines for fast processing and low delay variation in
Unstructured CES mode (1 VCC per port, for 8 UDT VCCs total)
Low latency in Unstructured CES mode provided by on-chip CDV buffering which does not require any
external memory
Internal CDV buffers of 2048 bytes for each UDT port
Maximum UDT CDV buffering of ± 4.9 ms in DS1 mode and ± 3.7 ms in E1 mode
External CDV buffers of 1024 bytes for each SDT port
Maximum SDT CDV buffering of ± 63.75 ms (dependent on the Reassembly Circular Buffer size and
number of channels per VC)
Non-CBR data cell transmission and reception for software-implemented SAR function (through non-CBR
Data Cell Buffers in external memory)
Gathers statistical information and provides management statistics for network management through
microprocessor interface
Low latency in segmentation and reassembly directions
Individual, per-port, integrated clock-recovery PLL allows for flexible, independent timing on each TDM port
Per-port Stratum 4 digital PLL supports several clock recovery modes:
Support for optional external PLL such as MT9042 or MT9044: primary & secondary network references and
primary & secondary LOS references output to external PLL; TDM_CLOCK input from external PLL
Bus clock I/O for operation in backplane mode: C4M/C2M and F0.
• Automatically eliminates null cells (i.e., VPI and VCI = 0)
• Look-up table supports up to 65536 VCC entries
• Per VCC monitoring compliant with ATMF CES specification Version 2.0 MIB
• Synchronous clocking - generates DS1 or E1 clock from network reference (19.44 MHz or 8 kHz)
• Adaptive clocking - recovers clock from received-data buffer fill-level
• SRTS - recovers clock from received RTS (residual time stamp) nibbles
• Line-rate clocking - PLL locks to incoming DS1 or E1 clock and reduces jitter
• Free-running clocks - PLL provides free-running high-accuracy clock for start-up or no-signal conditions (accuracy
• Direct control of PLL output frequency - offset from centre frequency can be configured via CPU
limited by MCLK accuracy)
Segmentation and Reassembly Modules
Clock Management
Zarlink Semiconductor Inc.
MT90520
15
Data Sheet