mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 49

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

It is also possible to loop the TDM data back by manually programming the TDM module to look for reassembly
data in the Segmentation Circular Buffers. The user can then switch channels between various ports.
4.4
The MT90520’s UTOPIA interface is compliant with the ATM Forum Level 2 specification for the UTOPIA interface
(af-phy-0039.000). The Level 2 specification is backwards-compatible with the Level 1 specification (af-phy-
0017.000); therefore, the MT90520 interface also supports Level 1 applications. The UTOPIA interface is capable
of emulating either a PHY device or an ATM device.
The MT90520’s UTOPIA interface addresses reference configuration A of Figure 14 when it is operating in ATM
mode. This means that the interface communicates with one, and only one, PHY. When the UTOPIA module is
operating in PHY mode, it addresses reference configuration B of Figure 14.
The UTOPIA module does not address multi-PHY (MPHY) operation in ATM mode, nor does it address the use of
multiple CLAV signals.
The UTOPIA interface allows the user to choose between an 8-bit or 16-bit interface. The 8-bit interface is only
specified to a maximum UTOPIA clock-rate of 33 MHz (in the UTOPIA Level 2 specification); however, the
MT90520 interface is capable of operating up to 52 MHz.
The user can choose to have the UTOPIA interface emulate a PHY device or an ATM device. When the MT90520
is operating in PHY mode, it is capable of being polled; this allows the ATM device accessing the MT90520 to
operate in multi-PHY mode.
The UTOPIA interface contains a loopback configuration, where data received on the incoming port can be looped
back to the outgoing port. This is implemented to assist developers with debug and diagnostics.
•
•
bits<5:1> - These five bits identify the input channel whose data is being output on the timeslot
associated with this entry.
bit<0> - This bit must be set to ‘1’ (the SDT Segmentation Circular Buffers onto which the SDT
Reassembly Circular Buffers are mapped always contain 64 entries).
UTOPIA Interface Module
A - 1 ATM and 1 PHY
MT90520
PHY
Figure 14 - UTOPIA Reference Configurations
Zarlink Semiconductor Inc.
MT90520
49
MT90520
ATM
B - 1 ATM and multiple PHYs
(optional)
PHY1
. . .
(optional)
PHY N
Data Sheet