zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 103

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

The ICL, the OCL bits and V/D bit only have an effect on PCM code translations for constant delay connections,
variable delay connections and per-channel message mode.
Note 1:
Note 2:
15 - 5
3 - 2
1 - 0
Bit
15
4
0
Refer to G.711 standard for detail information of different laws.
For proper
14
0
OCL1 - 0
ICL1 - 0
Unused
Name
V/D
13
0
Table 71 - Connection Memory High (CM_H) Bit Assignment
µ-
law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high.
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
Voice/Data Control
When this bit is low, the corresponding channel is for voice.
When this bit is high, the corresponding channel is for data.
Input Coding Law
Output Coding Law
11
0
OCL1
ICL1-
00
01
10
11
-0
00
01
10
11
0
10
0
Zarlink Semiconductor Inc.
9
0
For Voice (V/D bit = 0)
For Voice (V/D bit = 0)
µ-law w/o Magnitude
µ-law w/o Magnitude
CCITT.ITU A-law
CCITT.ITU µ-law
CCITT.ITU A-law
CCITT.ITU µ-law
ZL50018
A-law w/o ABI
A-law w/o ABI
8
0
Inversion
Inversion
103
7
0
Description
Output Coding Law
Input Coding Law
6
0
5
0
For Data (V/D bit = 1)
For Data (V/D bit = 1)
V/D
All Bits Inverted
All Bits Inverted
4
Inverted ABI
Inverted ABI
No code
No code
ABI
ABI
ICL
3
1
ICL
2
0
OCL
1
1
Data Sheet
OCL
0
0