zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 90

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

MML
External Read/Write Address: 006A
Reset Value: 0000
15
R3
Bit
11
10
9
8
7
6
5
4
3
2
1
0
MMU
14
R3
R2MMU
R1MMU
R0MMU
R2MML
R1MML
R0MML
R2MU
R1MU
R0MU
Name
R2ML
R1ML
R0ML
13
R3
ML
H
MU
12
R3
Table 58 - Reference Mask Register (RMR) Bits (continued)
Reference 2 Multi-period Lower Limit Mask Bit: When this bit is high, it masks the
multi-period lower limit check (or forces pass) for REF2.
Reference 2 Multi-period Upper Limit Mask Bit: When this bit is high, it masks the
multi-period upper limit check (or forces pass) for REF2.
Reference 2 Single-period Lower Limit Mask Bit: When this bit is high, it masks the
single-period lower limit check (or forces pass) for REF2.
Reference 2 Single-period Upper Limit Mask Bit: When this bit is high, it masks the
single-period upper limit check (or forces pass) for REF2.
Reference 1 Multi-period Lower Limit Mask Bit: When this bit is high, it masks the
multi-period lower limit check (or forces pass) for REF1.
Reference 1 Multi-period Upper Limit Mask Bit: When this bit is high, it masks the
multi-period upper limit check (or forces pass) for REF1.
Reference 1 Single-period Lower Limit Mask Bit: When this bit is high, it masks the
single-period lower limit check (or forces pass) for REF1.
Reference 1 Single-period Upper Limit Mask Bit: When this bit is high, it masks the
single-period upper limit check (or forces pass) for REF1.
Reference 0 Multi-period Lower Limit Mask Bit: When this bit is high, it masks the
multi-period lower limit check (or forces pass) for REF0.
Reference 0 Multi-period Upper Limit Mask Bit: When this bit is high, it masks the
multi-period upper limit check (or forces pass) for REF0.
Reference 0 Single-period Lower Limit Mask Bit: When this bit is high, it masks the
single-period lower limit check (or forces pass) for REF0.
Reference 0 Single-period Upper Limit Mask Bit: When this bit is high, it masks the
single-period upper limit check (or forces pass) for REF0.
MML
R2
H
11
MMU
10
R2
R2
ML
9
Zarlink Semiconductor Inc.
ZL50018
MU
R2
8
90
MML
R1
7
Description
MMU
R1
6
ML
R1
5
MU
R1
4
MML
R0
3
MMU
R0
2
Data Sheet
ML
R0
1
MU
R0
0