zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 79
zl50018gag2
Manufacturer Part Number
zl50018gag2
Description
2 K Digital Switch With Enhanced Stratum 3 Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50018GAG2.pdf
(136 pages)
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Note 1:
Note 2:
Note 1:
Note 2:
15 - 0
Reset Value: 3B9A
15 - 0
External Read/Write Address: 0050
External Read/Write Address: 0051
Reset Value: 9DE8
MFU
MFU
Bit
Bit
15
15
15
31
The default value represents far upper limit for all reference frequencies, which is +11.287 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
The name ’upper’ is based on frequency.
The default value represents far upper limit for all reference frequencies, which is +11.287 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
The name ’upper’ is based on frequency.
MFU
MFU
14
14
14
30
MFU15 - 0
MFU31 - 16
Name
Name
Table 44 - Multi-period Far Upper Limit Register - Lower 16 Bits (MPFULRL)
Table 45 - Multi-period Far Upper Limit Register - Upper 16 Bits (MPFULRU)
MFU
H
MFU
13
13
13
29
H
(Note 1)
(Note 1)
MFU
MFU
12
12
12
28
Multiple-Period Far Upper Limit Bits: Total binary value of these bits and the
MPFULRU register bits defines the far upper limit for the multiple period count of any
reference input, minus 1. The unit of the binary value is measured in 100 MHz clock
periods.
Multiple-Period Far Upper Limit Bits: Total binary value of these bits and the
MPFULRL register bits defines the far upper limit for the multiple period count of any
reference input, minus 1. The unit of the binary value is measured in 100 MHz clock
periods.
H
H
MFU
MFU
11
11
11
27
MFU
MFU
10
10
10
26
MFU
MFU
25
9
9
9
Zarlink Semiconductor Inc.
ZL50018
MFU
MFU
24
8
8
8
79
MFU
MFU
23
7
7
7
Description
Description
MFU
MFU
22
6
6
6
MFU
MFU
21
5
5
5
MFU
MFU
20
4
4
4
MFU
MFU
19
3
3
3
MFU
MFU
18
2
2
2
Data Sheet
MFU
MFU
17
1
1
1
MFU
MFU
16
0
0
0
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