zl50060gag2 Zarlink Semiconductor, zl50060gag2 Datasheet - Page 85
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zl50060gag2
Manufacturer Part Number
zl50060gag2
Description
16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 64 Input And 64 Output Streams Pin Compatible With Mt90869
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50060GAG2.pdf
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CK_int *
Note *: CK_int is the internal clock signal of 131.072MHz
Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the
Control Register.
(244ns)
(122ns)
(244ns)
(122ns)
(122ns)
frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the
FP16o
FP16o
(61ns)
FP8o
FP8o
C16o
FP8i
FP8i
C8o
C8i
Figure 25 - Input and Output Clock Timing Diagram for ST-BUS
t
OCL16
t
ICL
t
OCL8
t
t
IFPS244
OCH16
t
FPFBF8_244
t
FPFB16_61
t
IFPS122
t
t
FPFBF16_122
t
FPFBF8_122
ICH
t
OCH8
Zarlink Semiconductor Inc.
ZL50060/1
t
IFPW244
t
t
IFPW122
OFPW16_61
t
t
OFPW8_122
OFPW16_122
t
OFPW8_244
85
t
t
IFPH122
t
FBFPF16_122
OFBOS
t
FBFPF8_122
t
FBFP16_61
t
IFPH244
t
FBFPF8_244
t
ICP
t
OCP8
t
t
rOC16
rIC
t
rOC8
t
OCP16
t
fIC
t
t
fOC8
fOC16
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