zl50063 Zarlink Semiconductor, zl50063 Datasheet - Page 12

• Manufacturer Part Number: zl50063
• Description: 16k-channel Digital Switch With High Jitter Tolerance, Single Rate 32mbps , And 32 Inputs And 32 Output
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
JTAG Control Signals
Pin Name
RESET
TRST
TMS
TCK
R/W
DTA
TDo
TDi
DS
Coordinates
Package
(196-ball
ZL50063
PBGA)
B11
A11
B10
A12
A14
C8
A9
D9
C9
Data Strobe (5V Tolerant Input). This active LOW input works in conjunction
with CS to enable the microprocessor port read and write operations. Note
that a minimum of 30ns must separate the de-assertion of DTA (to high)
and the assertion of CS and/or DS to initiate the next access.
Read/Write (5V Tolerant Input). This input controls the direction of the data
bus lines (D0-D15) during a microprocessor access.
Data Transfer Acknowledgment (5V Tolerant Three-state Output). This
active LOW output indicates that a data bus transfer is complete. A pull-up
resistor is required to hold a HIGH level. Note that a minimum of 30ns must
separate the de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
Device Reset (5V Tolerant Input with Internal Pull-up). This input (active
LOW) asynchronously applies reset and synchronously releases reset to the
device. In the reset state, the outputs LSTo0-15 and BSTo0-15 are set to a
HIGH or high impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of this pin also clears
the device registers and internal counters. Refer to Section 7.3 on page 25
for the timing requirements regarding this reset signal.
Test Clock (5V Tolerant Input).
Provides the clock to the JTAG test logic.
Test Mode Select (5V Tolerant Input with Internal Pull-up).
JTAG signal that controls the state transitions of the TAP controller.
Test Serial Data In (5V Tolerant Input with Internal Pull-up).
JTAG serial test instructions and data are shifted in on this pin.
Test Serial Data Out (5V Tolerant Three-state Output).
JTAG serial data is output on this pin on the falling edge of TCK. This pin is
held in a high impedance state when JTAG is not enabled.
Test Reset (5V Tolerant Input with Internal Pull-up).
Asynchronously initializes the JTAG TAP controller to the Test-Logic-Reset
state. This pin must be pulsed LOW during power-up for JTAG testing. This
pin must be held LOW for normal functional operation of the device.
Zarlink Semiconductor Inc.
ZL50063
12
Description
Data Sheet