zl50063 Zarlink Semiconductor, zl50063 Datasheet - Page 39

• Manufacturer Part Number: zl50063
• Description: 16k-channel Digital Switch With High Jitter Tolerance, Single Rate 32mbps , And 32 Inputs And 32 Output
• Manufacturer: Zarlink Semiconductor

13.4
Addresses 0063
There are sixteen Backplane Input Delay Registers (BIDR0 to BIDR15).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR15 define the input bit and fractional bit delay of each Backplane stream. The possible
bit delay adjustment is up to 7
When the SMPL_MODE bit is HIGH, BIDR0 to BIDR15 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.
The BIDR0 to BIDR15 registers are configured as follows:
13.4.1
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7
period. The default sampling point is at the
This can be described as: no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 *
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (
refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from
Table 16 illustrates the bit delay and sampling point selection.
(where n = 0 to 15)
Backplane Input Bit Delay Registers (BIDR0 to BIDR15)
Backplane Input Delay Bits 4-0 (BID[4:0])
BIDRn Bit
BID4
0
0
15:5
4:0
Table 16 - Backplane Input Bit Delay and Sampling Point Programming Table
H
to 0072
BID3
0
0
Table 15 - Backplane Input Bit Delay Register (BIDRn) Bits
H
3
BIDn
BID2
/
4
0
0
Reserved
bits, in steps of
BID[4:0]
Name
BID1
0
0
1
/
3
4
/
4
to
Reset
Value
Zarlink Semiconductor Inc.
bit location.
4
0
0
1
/
BID0
/
4
4
ZL50063
in
0
1
bit.
1
/
Reserved
Must be set to 0 for normal operation
Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit fractional delay value (0 to 7
When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (
refers to the integer bit delay value (0 to 7 bits).
4
39
bit increments.
SMPL_MODE
Input Data
0 (Default)
Bit Delay
= LOW
1/4
3
/
4
bit periods forward, with resolution of
1
/
4
= 4
3
Input Data
0 (Default)
Bit Delay
/
Description
4.
0
SMPL_MODE
= HIGH
Input Data
1
Sampling
/
4
Point
to
1
3/4
4/4
/
4
4
to
/
4
Data Sheet
). BID[4:2]
4
/
4
). BID[4:2]
3
1
/
/
4
4
).
bit