zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 30

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

3.1.5
TDM_CLKi_REF
TDM_CLKo_REF
TDM_FRMi_REF
TDM_FRMo_REF
Signal
TDM Signals Common to ZL50110, ZL50111, ZL50112 and ZL50114
I/O
I D
I D
O
O
C3
E6
C2
B1
Table 6 - TDM Interface Common Pin Definition
Package Balls
ZL50110/11/12/14
Zarlink Semiconductor Inc.
30
TDM port reference clock input for
backplane operation
TDM port reference clock output for
backplane operation
TDM port reference frame input. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0i
H.110:
H-MVIP:
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
TDM port reference frame output. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0o
H.110:
H-MVIP:
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
TDM_FRAME
TDM_FRAME
TDM_F0
TDM_F0
Description
Data Sheet