zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 72

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

7.8
The JTAG interface is used to access the boundary scan logic for board level production testing.
7.9
7.9.1
ZL50110/11/12/14 family offers direct connection to PowerQUICC™ II (MPC8260) host processor and associated
memory, but can support other processors with appropriate interface logic.
7.9.2
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7.10
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TDM Framers and/or Line Interface Units
Ethernet PHY for each MAC port
Optional ZBT-SRAM for extended packet memory buffer depth
System clock speed of 100 MHz
Host clock speed of up to 66 MHz
Debug option to freeze all internal state machines
JTAG (IEEE1149) Test Access Port
3.3 V I/O Supply rail with 5 V tolerance
1.8 V Core Supply rail
Fully compatible with the MT90880/1/2/3 Zarlink products
JTAG Interface and Board Level Test Features
External Component Requirements
Miscellaneous Features
Host Processor
Other components
SCLK
V
RST
DD
<0.5 V
DC
Figure 24 - Powering Up the ZL50110/11/12/14
ZL50110/11/12/14
Zarlink Semiconductor Inc.
10 ns
72
> 100 µs
Core supply (1.8 V)
I/O supply (3.3 V)
Data Sheet
t
t
t