am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 63

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

Interface
To use a Flash-type device with the PCnet-ISA
II controller, Flash Select is set in register 0F0h of the
Plug and Play registers. Flash Select is cleared
by RESET (default).
In bus master mode, BPCS becomes Flash_OE and
IRQ12 becomes Flash_WE. The Flash ROM devices
CS pin is connected to ground.
In shared memory mode, BPCS becomes Flash_CS
and IRQ12 becomes the static RAM Chip Select, and
the SROE and SRWE signals are connected to both
the SRAM and Flash devices.
Optional IEEE Address PROM
Normally, the Ethernet physical address will be stored
in the EEPROM with the other configuration data. This
reduces the parts count, board space requirements,
and power consumption. The option to use a standard
parallel 8 bit PROM is provided to manufacturers who
a r e c o n c e r n e d a b o u t t h e n o n -vo l a t i l e n a t u r e
of EEPROMs.
To use a 8 bit parallel PROM to store the IEEE address
data instead of stor ing it in the EEPROM, the
APROM_EN bit is set in the Plug and Play registers by
the EEPROM upon RESET. IRQ15 is redefined by the
setting of this bit to be APCS, or ADDRESS PROM
CHIP SELECT. This pin is connected to an external 8
bit PROM, such as a 27LS19. The address pins of the
PROM are connected to the lower address pins of the
ISA bus, and the data lines are connected to the private
data bus.
In this mode, any accesses to the IEEE address will be
passed to the external PROM and the data will be
passed through the PCnet-ISA II controller to
the system data bus.
EISA Configuration Registers
The PCnet-ISA II controller has support for the 4-byte
EISA Configuration Registers. These are used in EISA
systems to identify the card and load the appropriate
configuration file for that card. This feature is enabled
using bit 10 of ISACSR2. When set to 1, the EISA
Configuration registers will be enabled and will be
read at I/O location 0xC80–0xC83. The contents of
these 4 registers are stored in the EEPROM and are
automatically read in at RESET.
Bus Interface Unit (BIU)
The bus interface unit is a mixture of a 20 MHz state
machine and asynchronous logic. It handles two types
of accesses; accesses where the PCnet-ISA II control-
ler is a slave and accesses where the PCnet-ISA II con-
troller is the Current Master.
In slave mode, signals like IOCS16 are asserted and
deasser ted as soon as the appropr iate inputs
Am79C961A
are received. IOCHRDY is asynchronously driven
LOW if the PCnet-ISA II controller needs a wait state. It
is released synchronously when the PCnet-ISA II con-
troller is ready.
When the PCnet-ISA II controller is the Current Master,
all the signals it generates are synchronous to the
on-chip 20 MHz clock.
DMA Transfers
The BIU will initiate DMA transfers according to the
type of operation being performed. There are three pri-
mary types of DMA transfers:
1. Initialization Block DMA Transfers
During initialization, the PCnet-ISA II transfers 12
words from the initialization block in memory to internal
registers. These 12 words are transferred through dif-
ferent bus mastership period sequences, depending on
whether the TIMER bit (CSR4, bit 13) is set and, if
TIMER is set, on the value in the Bus Activity Timer
register (CSR82).
If the TIMER bit is reset (default), the 12 words are
always transferred during three separate bus master-
ship periods. During each bus mastership period, four
words (8 bytes) will be read from contiguous memory
addresses.
If the TIMER bit is set, the 12 words may be transferred
using anywhere from 1 to 3 bus mastership periods,
depending on the value of the Bus Activity Timer regis-
ter (CSR82). During each bus mastership period, a
minimum of four words (8 bytes) will be read from con-
tiguous memory addresses. If the TIMER bit is set and
the value in the Bus Activity Timer register allows it, 8
or all 12 words of the initialization block are read during
a single bus mastership period.
2. Descriptor DMA Transfers
Descriptor DMA transfers are performed to read or
write to transmit or receive descriptors. All transmit and
receive descriptor READ accesses require 3 word
reads (TMD1, TMD0, then TMD2 for transmit descrip-
tors and RMD1, RMD0, then RMD2 for receive descrip-
tors). Transmit and receive descr iptor WRITE
accesses to unchained descriptors or the last descrip-
tor in a chain (ENP set) require 2 word writes (TMD1
then TMD3 for transmit and RMD1 then RMD3 for re-
ceive). Transmit and receive descriptor WRITE ac-
cesses to chained descriptors that do not have ENP set
require 1 word write (TMD1 for transmit and RMD1 for
receive). During descriptor write accesses, only the
bytes which need to be written are written, as con-
trolled by the SA0 and SBHE pins.
If the TIMER bit is reset (default), all accesses during a
single bus mastership period will be either all read or all
write and will be to only one descriptor. Hence, when
the TIMER bit is reset, the bus mastership periods for
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