am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 76

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
r e c t i o n c i r c u i t . T h i s c i r c u i t e n s u r e s t h a t t h e
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI inputs
after IRXCRS is asserted for an end of message.
IRXCRS de-asserts 1 to 2 bit times after the last posi-
tive transition on the incoming message. This initiates
the end of reception cycle. The time delay from the last
rising edge of the message to IRXCRS deassert allows
the last bit to be strobed by IRXCLK and transferred to
the controller section, but prevents any extra bit(s) at
the end of message. When IRXCRS de-asserts an
IRXCRS hold off timer inhibits IRXCRS assertion for at
least 2 bit times.
Data Decoding
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the DI inputs. Input
error is less than 35 mV to minimize sensitivity to input
rise and fall time. IRXCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following IRXCLK. The data receiver also
generates the signal used for phase detector compari-
son to the internal MENDEC voltage controlled
oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI )
should be externally terminated by two 40.2
resistors and one optional common-mode bypass
capacitor, as shown in the Differential Input Termina-
tion diagram below. The differential input impedance,
Z
76
IDF
, and the common-mode input impedance, Z
DI
*Internal signal
Receiver
Reject
Data
Noise
Filter
Receiver Block Diagram
ICM
Am79C961A
1%
,
phase-locked clock remains locked on the received
signal. Individual bit cell phase corrections of the
Voltage Controlled Oscillator (VCO) are limited to 10%
of the phase difference between BCC and phase-
locked clock.
are specified so that the Ethernet specification for cable
termination impedance is met using standard 1%
resistor terminators. If SIP devices are used, 39
the nearest usable equivalent value. The CI differen-
tial inputs are terminated in exactly the same way as
the DI pair.
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI inputs.
This collision signal passes through an input stage
which detects signal levels and pulse duration. When
the signal is detected by the MENDEC it sets the inter-
nal collision signal, ICLSN, HIGH. The condition contin-
PCnet-ISA II
Manchester
Decoder
Carrier
Detect
Circuit
Differential Input Termination
DI+
DI
40.2
IRXDAT*
IRXCLK*
IRXCRS*
0.01 F
to 0.1 F
40.2
AUI Isolation
Transformer
19364A-17
19364B-16
is