am79c850 Advanced Micro Devices, am79c850 Datasheet

am79c850

Manufacturer Part Number

am79c850

Description

Supernet-r 3

Manufacturer

Advanced Micro Devices

Datasheet

1.AM79C850.pdf (97 pages)

Current page: 1 of 97
Download datasheet (342Kb)

Am79C850

SUPERNET 3

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL OVERVIEW

SUPERNET 3 is a 208-pin CMOS integration of FDDI

MAC, PHY, Address Filter, and clock generation and

recovery functions. It is the third generation FDDI

offering from AMD which integrates the SUPERNET 2

family of chips into a single-chip solution. Refer to the

SUPERNET 2 data book (PID 15502C) for basic

feature descriptions.

The SUPERNET 3 is backward compatible to the

SUPERNET 2 Tag Mode of operation in which the

SUPERNET 3 buffer memory interface logic maintains

the buffer memory as multiple FIFOs.

The SUPERNET 3 provides DMA channels, arbitrates

access to the network buffer memory, and controls the

data path between the buffer memory and the medium.

The MAC also implements the timed-token protocol and

receive/transmit control as specified for the Media

Access Control (MAC) sublayer of the ISO standard

9314-2 for FDDI. The Physical Layer functions defined

by the ISO 9314-1 are performed by the SUPERNET 3.

SUPERNET 3 implements on-chip digital clock

recovery and transmit functions for fiber. To support

copper media, the PHY-PMD interface is maintained

and an external module can be implemented in

the same footprint as the fiber optic transceiver to

perform the MLT-3 encoding/decoding and equaliza-

tion. SUPERNET 3 integrates the scrambler and

descrambler

copper media.

This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended

to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Compliant with the ANSI X3T9.5/ISO 9314

specification

— 100 Mbps data rate

— Timed token-passing protocol

— Ring topology

Complete memory management

— Supports 256K bytes of local frame buffer

— Supports buffer memory bandwidths of

— Tag-Mode: minimum latency/highest

memory

200 Mbps and 400 Mbps

performance buffer memory management, ideal

for adapter card designs

PRELIMINARY

functions

for

transmissions

over

SUPERNET 3 FEATURES UPDATE

The basic feature description for SUPERNET 3 is

provided in the SUPERNET 2 data book. The enhanced

features are as listed below:

ANSI-compliant TP-PMD Stream Cipher

Scrambling/Descrambling

Full duplex operation: 200 Mbps continuous

data rate

Supports both fiber optic and copper twisted-

pair media

Diagnostic features

— Built in Self Test (BIST) in Address Filter,

Hardware Physical Connection Management

support

Low power consumption—reduction of more

than 25% from SUPERNET 2 solution

This is a CMOS integration of the redesigned

FORMAC Plus, an enhanced PLC, a 32-entry

address filter (AF, which is based on a Content

Addressable Memory, or CAM, core), and a CMOS

PDX core for clock and data recovery.

A 32-entry, extensible and fully maskable AF

allows additional individual and group addresses to

be supported.

The physical data transmitter and receiver (PDX)

circuits are also embedded on-chip using

proprietary digital clock-recovery technology.

For the purposes of implementing copper PMD,

the scrambler/descrambler functions are

embedded within the chip.

The Buffer Memory interface has been modified to

support slower SRAM’s (35 ns) without affecting

backward compatibility with SUPERNET 2.

SUPERNET 3 supports the FDDI single

attachment station (SAS) but is capable of

supporting a dual attachment station (DAS)

Physical Layer Controller with Scrambler

Publication# 19574

Issue Date: April 1995

Rev. A

Advanced

Devices

Amendment /0

Micro

Related parts for am79c850

Related keywords

am79c850 datasheet
am79c850 data sheet
am79c850 pdf datasheet
am79c850 component
am79c850 part
am79c850 distributor
am79c850 RoHS
am79c850 datasheet download