am7992b Advanced Micro Devices, am7992b Datasheet
am7992b
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am7992b Summary of contents
Page 1
... Carrier/collision detected for inputs greater than –275 mV — No carrier/collision for inputs less than –175 mV GENERAL DESCRIPTION The Am7992B Serial Interface Adapter (SIA Manchester encoder/decoder compatible with IEEE 802.3, Cheapernet, and Ethernet specifications IEEE 802.3/Ethernet application, the Am7992B inter- ...
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... TCLK Transmit– TENA 12 13 03378I-2 Note: Pin 1 is marked for orientation (ILACC ) PLCC RCLK TSEL 8 GND1 GND2 Am7992B AMD Receive- 25 TEST CC1 CC2 03378I-3 ...
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... P = 24-Pin (Slim) Plastic DIP (PD3024) SPEED Not Applicable Valid combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am7992B Valid Combinations 3 ...
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... LOW during transmission. At the end of transmission the open collector output is disabled, allowing TSEL to rise and provide a smooth transmission from logic HIGH to “zero” differential idle. Delay and output return to zero are externally controlled by the RC network at TSEL and Transmit load inductance. Am7992B terminated ...
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... When TEST is grounded enabled and RCLK is enabled except during clock acquisition, when RCLK is HIGH. GND1 High Current Ground GND2 Logic Ground gain is 1.25 TCLK GND3 Voltage-Controlled Oscillator Ground V CC1 High Current and Logic Supply V is internally lim- CC2 CO Voltage-Controlled Oscillator Supply CO Am7992B for Am7992B ...
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... FUNCTIONAL DESCRIPTION The Am7992B serial interface adapter (SIA) has three basic functions Manchester encoder/line driver in the transmit path, a Manchester decoder with noise filtering and quick lock-on characteristics in the receive path, and a signal detector/converter (10 MHz differen- tial to TTL) in the collision path. In addition, the SIA pro- ...
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... ALS Driver or Equivalent Figure 3. TTL Clock Driver Circuit for X SIA Oscillator Specification for External Crystal When using a crystal to drive the Am7992B oscillator, the following crystal specification should be used to en- sure a transmit accuracy of 0.01%: Limit Min Nominal Resonant Frequency –50 Error with C ...
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... Manchester data. It also controls the stop and start of the phase-locked loop during clock ac- quisition. In the Am7992B, clock acquisition requires a valid Manchester bit pattern of 1010 to lock on the in- coming message (see Receive Timing—Start of Re- ception Clock Acquisition waveform diagram) ...
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... MHz signal at the Collision inputs. This collision signal passes through an input stage that de- tects signal levels and pulse duration. When the signal is detected by the Am7992B, it sets the CLSN line HIGH. This condition continues for approximately 160 ns after the last LOW-to-HlGH transition on Collision ...
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... Manchester data at clock acquisition, and average val- ues for clock leading jitter tolerance are 21.5 ns. For cases 5 through 8, average values are 24.4 ns. Cases 5 through 8 are jittered at bit times applica- ble. The Am7992B, then, has on average 0.6 ns static phase error for the noise-free case. Am7992B ...
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... CHEAPERNET Local Local CPU Memory Local Bus AUI Cable DTE Am7990 Am7992B LANCE SIA DTE Am7990 Am7992B LANCE SIA Figure 7. Typical ETHERNET Node Am7992B MAU TAP Am7996 Transceiver Power Supply ETHERNET COAX Am7996 RG58 Transceiver BNC “T” Power Supply 03378I-11 11 ...
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... Commercial (C) Devices Temperature ( +70 C Supply Voltage (V +7.0 V Operating ranges define those limits between which the func- –0 Max CC tionality of the device is guaranteed. +5.5 V – +16 V – +25 mA 100 +16 V Am7992B AMD ) . . . . . . . . . . . . . . . . . + +5.0 V 10% CC ...
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... Max – Min 2 0 (Note 3) (Note 3) Am7992B Com’l Min Max = Min 2 Min 0.5 = Min 0.4 550 770 –550 –770 (Note 1) –20 20 (Note 2) –0.5 0 (Note 1) 20 2.0 = 2.7 V +50 0.8 = 0.4 V – ...
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... Input Pulse Width to Turn-On Max|) IDC Input Pulse Width to Turn-Off Max|) IDC Input Pulse Width to Not Max|) IDC Max on IDC to CLSN ) H Max on IDC to CLSN ) L Am7992B AMD Test Conditions Min Max 85 118 (Note (Note 9) 300 (Note 10) ...
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... Test correlated to T TCH 12. Measured from 50% point of X1 driving the input in production test. Output, (Bit Cell Center to Edge) Output Output Rise Time Output Fall Time . OFF = V OFF Am7992B Test Conditions Min Max (Note 11 (Note 1) 5 49.5 50.5 100 4 20% – ...
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... Will be Steady Steady May Will be Change Changing from from May Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Am7992B AMD KS000010 ...
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... E. Timing Diagram does not include Internal Propagation Delays. F. First valid data at RX (Bit 5). Receive Timing – Start of Reception Clock Acquisition Bit Cell 2 Bit Cell 3 Bit Cell BCB BCC BCB BCC BCB BCC 0 1 (Note D) 15 Am7992B Bit Cell BCB BCC BCB 0 1 (Note C) (Note F) 03378I-12 17 ...
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... INTRCLK RCK Enable RCLK RX PLL CLK Notes: A. INTCARR deasserts 1.55 bit times after last Receive Rising Edge. B. Start of Next Packet. Receive Timing – End of Reception (Last Bit = Bit N BCB BCC BCB 17 Bit (N – 1) Bit N Am7992B AMD (Note B) (Note 03378I-13 ...
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... Differentially) BCC INTCARR V Enable INTRCLK RCK Enable RCLK RX RENA PLL CLK Note: A. INTCARR deasserts 1.55 bit times after last Receive Rising Edge. Receive Timing – End of Reception (Last Bit = 1) 1 Bit N BCB BCC (Note A) 17 Bit (N – 1) Bit N 11 Am7992B 16 03378I-14 19 ...
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... MHz Sine Wave from Crystal Oscillator or driven with X1 driven from External Source Waveform. B. TSEL connected as shown in Figure 2B. For Figure 2A, Transmit+ is HIGH when TENA is LOW. C. When Idle Transmit Zero Differential is 1 Transmit Timing – Start of Packet Am7992B AMD 03378I-15 ...
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... V O Transmit (Measured Differentially *TSEL Components (see Figure 2B). See Typical Performance Curve for Response at End of Transmission with Inductive Loads Bit (N – 1) Bit N BCB BCC BCB BCC BCB Transmit Timing – End of Transmission* Am7992B 0 0 03378I-16 21 ...
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... SWITCHING WAVEFORMS 0 V Collision Presence – 22 CLSN X1 TCLK TENA Transmit (Measured Differentially Max IDC 2.0 V Collision Timing Transmit Timing (at start of packet) Am7992B AMD V Max IDC 03378I-17 80% 20% 20% 33 03378I-18 80% 50% 32 ...
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... IRVD 2.0 V Receive Input Pulse Width Timing V IRVD 2.0 V Collision Input Pulse Width Timing 1 3 0 2 RCLK and RX Timing Am7992B +1 –1.5 V IRVD 03378I-19 +1 –1.5 V IRVD 03378I-20 03378I-21 23 ...
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... Specification for External TTL Level in Functional Description section 2.0 V 0.8 V 0 2.0 2.0 0.8 0.8 28 2.0 V 0.8 V TCLK and TX Timing T OSC 1.5 1 LOW 2.0 34 ‘A’ ‘B’ BCC BCB (Bit Cell Center) (Bit Cell Boundary) X1 Driven from External Source Am7992B AMD 03378I-22 2.0 1.5 0 03378I-23 ...
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... Rising bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 4 uses bit 5, Case 8 uses bit 55 BCB BCC BCC BCC BCC 1/4 Bit Cell 0 V tEJI tEJ51 1/4 Bit Cell Input Jitter Timing Am7992B BCC BCC BCC BCC 4.5 V Strobe RX tEJI A ...
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... Test Load: 2. 802.3 10BASE5 Network Connection: 3. 802.3 10BASE2 Network Connection 1.0 2.0 3.0 Time ( Test Am7992B 75 H NOM. AUI Am7992B 95 H 80.4 Am7992B AMD 2 1 4.0 5.0 6.0 03378I-25 L Test Am7996 75 H NOM. 80 Am7996 V O 03378I-26 ...
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... AMD SWITCHING TEST CIRCUITS DUT 50 pF 03378I-27 A. Test Load for RX, RENA, RCLK, TCLK, CLSN DUT Transmit+ DUT Transmit– B. Transmit Output + – DC Voltage C. Receive and Collision Input Am7992B 03378I-28 03378I-29 27 ...