am7992b Advanced Micro Devices, am7992b Datasheet - Page 9

• Manufacturer Part Number: am7992b
• Description: Serial Interface Adapter Sia
• Manufacturer: Advanced Micro Devices

last rising edge of the message to INTCARR deassert
allows the last bit to be strobed by RCLK and trans-
ferred by the LANCE without an extra bit at the end of
the message. When RENA deasserts (see Receive
Timing—End of Reception waveform diagrams), a
RENA hold-off timer inhibits RENA assertion for at
least 120 ns.
Data Decoding
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the Receive inputs.
Input error (VIRD) is less than 35 mV to minimize sen-
sitivity to input rise and fall time. RCLK strobes the data
receiver output at 1/4 bit time to determine the value of
the Manchester bit and clocks the data out at RX on the
following RCLK. The data receiver also generates the
signal used for phase detector comparison to the inter-
nal Am7992B V
Notes:
1. Connect R1, R2, C1, C2 for 0 differential nontransmit. Connect to ground for logic 1 differential nontransmit.
2. Pin 20 shown for normal device operation.
3. The inclusion of C4 and C5 is necessary to reduce the common-mode loading on certain transceivers that are direct
4. C2 reduces the amount of noise from the power supply and crosstalk from RCLK that can be coupled from TSEL through to
0.005% Accuracy
coupled.
the transmit outputs.
Parallel Mode.
Crystal 50 pF
20 MHz
C
2
CO
.
20 pF
R
1
510
V
CC
100 pF
C
R
1
2
Figure 6. External Component Diagram
100 pF
3 K
680 pF
10
11
12
1
2
3
4
5
6
7
8
9
CLSN
RX
RENA
RCLK
TSEL
GND1
GND2
X1
X2
TX
TCLK
TENA
Am7992B
Differential l/O Terminations
The differential input for the Manchester data
(Receive ) is externally terminated by two 40.2-ohm
capacitor. The differential input impedance, Z
the common-mode input, Z
Ethernet specification for cable termination impedance
is met using standard 1% resistor terminators. The Col-
lision differential inputs are terminated in exactly the
same way as the receive inputs (see Figure 6).
Collision Detection
A transceiver detects collisions on the network and
generates a 10 MHz signal at the Collision inputs. This
collision signal passes through an input stage that de-
tects signal levels and pulse duration. When the signal
is detected by the Am7992B, it sets the CLSN line
HIGH. This condition continues for approximately
160 ns after the last LOW-to-HlGH transition on
Collision .
1% resistors and one optional common-mode bypass
Collision+
Collision–
Transmit+
Transmit–
Receive+
Receive–
GND3
TEST
V
V
CC1
CC2
RF
PF
24
23
22
21
20
19
18
17
16
15
14
13
40.2
40.2
40.2
40.2
4700 pF
lCM
, are specified so that the
0.1 F
1%
1%
1%
1%
B
A
4.7 F
C
V
0.1 F
4
CC
0.1 F
0.1 F
03378I-10
lDF
C
5
and
9