am79q02 ETC-unknow, am79q02 Datasheet - Page 47
![no-image](/images/no-image-200.jpg)
am79q02
Manufacturer Part Number
am79q02
Description
Quad Subscriber Line Audio-processing Circuit Qslac Devices
Manufacturer
ETC-unknow
Datasheet
1.AM79Q02.pdf
(68 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
am79q021JC
Manufacturer:
AMD
Quantity:
12
Company:
Part Number:
am79q021JC
Manufacturer:
AMD
Quantity:
5 510
Part Number:
am79q021JC
Manufacturer:
AMD
Quantity:
20 000
Company:
Part Number:
am79q021VC
Manufacturer:
AMD
Quantity:
13 888
Company:
Part Number:
am79q02JC
Manufacturer:
ST
Quantity:
5 510
30. Read Revision Code Number (RCN)
31, 32. Write/Read GX Filter Coefficients
33, 34. Write/Read GR Filter Coefficients
(73h)
(80/81h)
R/W = 0: Write
R/W = 1: Read
(82/83h)
R/W = 0: Write
R/W = 1: Read
This command returns an 8-bit number (RCN) describing the revision number of the QSLAC
device. This command does not depend on the state of the Channel Enable Register.
The coefficient for the GX filter is defined as:
Power Up and Hardware Reset (
Note: The default value is contained in a ROM register separate from the programmable coefficient RAM.
There is a filter enable bit in Operating Functions Register to switch between the default and programmed
values.
The coefficient for the GR filter is defined as:
Power Up and Hardware Reset (
See note under Commands 31 and 32.
Command
I/O Data
Command
I/O Data Byte 1
I/O Data Byte 2
Command:
I/O Data Byte 1
I/O Data Byte 2
H
H
GX
GR
=
=
1
C10 2
+
(
C10
•
RCN7
C40
C20
C40
C20
–
D
D
D
0
1
1
m10
7
7
7
•
SLAC Products
2
{
–
1
m10
+
RST
RST
RCN6
{
C20 2
D
D
1
D
1
0
0
6
6
) Values = A9F0 (Hex) (H
6
) Values = 23A1 (Hex) (H
+
•
C20 2
–
m20
RCN5
m40
m20
m40
m20
•
D
D
D
1
0
0
[
5
5
5
–
1
m20
+
C30 2
[
1
RCN4
+
D
D
D
1
0
0
•
4
4
4
C30 2
–
m30
•
RCN3
(
C30
C10
C30
C10
–
GR
D
D
GX
D
1
0
0
0
m30
3
3
3
+
= 1.995 (6 dB)).
= 0.35547 (–8.984 dB)).
C40 2
(
1
+
RCN2
•
C40 2
D
D
D
0
0
0
–
2
2
2
m40
•
MPI Command
MPI Command
MPI Command
)
–
]
m40
}
RCN1
m30
m10
m30
m10
D
D
D
1
0
1
)
1
1
1
]
}
)
RCN0
R/W
R/W
D
D
D
1
0
0
0
47