80ksbr201 Integrated Device Technology, 80ksbr201 Datasheet

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80ksbr201

Manufacturer Part Number
80ksbr201
Description
High-speed Serial Rapidio 1x Or 4x Lanes Up To 10 Gbps High Speed Buffer. Expandable To 90mb With The Addition Of External Qdr Sram
Manufacturer
Integrated Device Technology
Datasheet
Device Overview
connect up to two high-speed Serial RapidIO interfaces. This device is
built to work with any sRIO device and especially with the IDT Pre-
Processing Switch (PPS), IDT70K2000. The SerB performs buffering
and off-loading of data as well as buffer-delay of data samples in various
applications. This device can act as either a slave, waiting for other
devices to read from it, or as a master in which the SerB writes data to a
programmed location once some criteria have been meet. This combi-
nation of storage and flexibility make it the perfect buffering solution for
sRIO systems.
Features
Block Diagram
„2007 Integrated Device Technology, Inc. All rights reserved.
The
– sRIO to sRIO
– sRIO to Parallel
– Parallel to sRIO
– Up to 288 Mbit external QDR SRAM
– 200 MHz; 18M, 36M, 72M, 144M or 288 M
– Internal and external memory functions as a single buffer
Two Independent Serial RapidIO Ports
Partial Bridging Functions
Configurable Queues and Sizes
Single/Dual Port Buffering
Optional External QDR SRAM Available
Seamless Integration of External and Internal Memory
IDT80KSBR201
is a high speed Serial Buffer (SerB) that can
sRIO SERIAL BUFFER
FLOW-CONTROL DEVICE
Figure 1. SerB Block Diagram
1 of 7
– Full, Empty, Partially Empty, Partially Full
– Serial Buffer can Either Send a Flag or Transmit Data at a
– One four-bit (x4) link, configurable to one-bit (x1) link
– Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps
– Short haul or long haul reach for each PHY speed
– Error management supports standard and enhanced port
– sRIO version 1.3
– Class 1+ End Point Device
– Support for an optional external microprocessor or FPGA
– Supports QDRII Burst of 2 Interface
– Supports Packet or Raw-data format
– One I
– JTAG Functionality for boundary scan and programming
– 1.2V Core operation with 3.3/2.5V JTAG interface
– 23mm x 23mm, 1.0mm ball pitch
Provides Status Flags for Combined Internal/External
Memories
Direct or polled operation of flag status bus
Optional Water mark
Interface - Serial Rapid IO (sRIO)
Interface - Parallel Port
Interface - I
Interface - JTAG
10 Gbps Throughput
High-Speed CMOS Technology
Package: 484-pin Plastic Ball Grid Array
Specific Packet Count or Byte Count
operations
2
C port for maintenance and error reporting
2
C Interface Port
November 26, 2007
Product Brief
80KSBR201

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80ksbr201 Summary of contents

Page 1

... Core operation with 3.3/2.5V JTAG interface ◆ Package: 484-pin Plastic Ball Grid Array – 23mm x 23mm, 1.0mm ball pitch Figure 1. SerB Block Diagram Product Brief 80KSBR201 Specific Packet Count or Byte Count operations 2 C Interface Port 2 C port for maintenance and error reporting ...

Page 2

... Buffer and Pre-Processing Switch”. The 80KSBR201 This device can operate as a master or a slave. In the sRIO environment, a master is defined as a device that origi- nates data transfers, either to or from that device. A slave is one that responds to commands from other devices to move data ...

Page 3

... S-Port 2 would have the same ability to send data in on S-Port 2, sending S-Port 1 or holding it for retrieval on S-Port 2, or both. „2007 Integrated Device Technology, Inc. All rights reserved. The SerB's primary application with the PPS will be to broadcast data. It must be a master to perform a broadcast, even if the data is requested ...

Page 4

... In this application, the SerB will sit between two FPGAs and offer buffering capability between the two devices. This application may or may not use the external memory. The SerB may act as either the initiator or receiver on both ports. „2007 Integrated Device Technology, Inc. All rights reserved. High ...

Page 5

... This is similar to the sRIO translation configuration except the SerB isolates the two ports. The device on S-Port 1 is not aware of the device on S-Port 2 (or P-Port). „2007 Integrated Device Technology, Inc. All rights reserved. High Queue 4 ...

Page 6

... The address bits on P-Port is used to select sRIO commands and destination IDs, along with the queue selections. In addition, the SerB may be used as a passive memory between S-Port 1 and P-Port, the same as described earlier between S-Port 1 and S-Port 2. „2007 Integrated Device Technology, Inc. All rights reserved. Figure 7. The sRIO device may initiate a command. That command will be picked ...

Page 7

... Brief datasheets are informational only” and are subject to change without notice. 5.0 Ordering Information For specific speeds, packages and powers, contact your sales office CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 „2007 Integrated Device Technology, Inc. All rights reserved. for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com ...

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