80ksbr201 Integrated Device Technology, 80ksbr201 Datasheet - Page 4

• Manufacturer Part Number: 80ksbr201
• Description: High-speed Serial Rapidio 1x Or 4x Lanes Up To 10 Gbps High Speed Buffer. Expandable To 90mb With The Addition Of External Qdr Sram
• Manufacturer: Integrated Device Technology

„2007 Integrated Device Technology, Inc. All rights reserved.
IDT
Notes
2.2 FPGA Offload Device
additional external memory. Since most FPGAs will avoid unnecessary intelligence, the SerB must be able to accept
simple commands with little overhead.
2.3 Buffer between Two Busses
directly from one port to the other, or data that enters one port may be fed back to the same port.
whenever data is received by the SerB, the SerB shall attempt to send the data to its final destination as soon as a
complete packet has been received. As a passive device, the SerB shall receive data and respond to any requests on any
port, but all received data shall be stored until transmission is requested by the destination port.
2.3.1 FPGA to FPGA Buffer
application may or may not use the external memory. The SerB may act as either the initiator or receiver on both ports.
In this application, the SerB will connect directly to an FPGA and act as a FIFO. This application may or may not use
All of the following applications involve the SerB sitting between two busses. In this configuration, data may be passed
For each of these configurations, the SerB may be programmed to be active or passive device. As an active device,
In this application, the SerB will sit between two FPGAs and offer buffering capability between the two devices. This
PPS
Speed
Serial
sRIO
Lines
High
Figure 4. PPS Combined with an FPGA (Distributed)
Figure 5
4 of 7
shows a diagram of this application.
Queue 5
Queue 2
Interface
External
Memory
QDR2 SRAM
High
Speed
Serial
Lines
sRIO
FPGA
November 26, 2007
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