mh2080 Music Semiconductors, Inc., mh2080 Datasheet - Page 2

• Manufacturer Part Number: mh2080
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

GENERAL DESCRIPTION
The HARRP MH2080 is a 8K deep 64bit wide CAM with
a 32-bit wide data interface and 32-bit ternary compare
instruction. The device is designed for use in layer 3
switches, routers, and layer 2 switches to provide very
high throughput address translation using tables held in
external RAM. The MH2080 has a fully deterministic
search time, independent of the size of the list and the
position of the data in the list. This unique feature
guarantees that the wire speed address recognition does
not impact the latency or induce some jitter on the latency
of the global system. Address fields from the packet
header are compared against a list of entries stored in the
OPERATIONAL OVERVIEW
The HARRP MH2080 is designed to act as an address
translator for lookup tables in layer 3 switches, routers, and
layer 2 switches. Refer to Figure 2 for a simplified block
diagram of a switch. During normal operation, the controller
extracts the address information from an arriving packet to
form the comparand, which is then compared against the
contents of the MH2080. The MH2080 generates an index
that is used to access the data in an external RAM, which
holds the destination port for accessing the network. The
controller reads the data from the RAM and forwards the
packet.
A unique feature of the MH2080 is its ternary comparison
that processes IPv4 CIDR addresses in a single cycle. The
bits of each MH2080 word are paired, such that each pair can
contain two binary values (0,1) or one ternary (0,1,X= "Don't
Care") value. A ternary value uses two bits, pairing bit n from
the first 32 bits (31-0) with bit n+32. When storing a ternary 0
or 1, the value to be stored is written into bit n (0<=n<=31),
and the complement of the value is written to bit n+32. Thus,
a ternary 0 written to ternary pair 7 would consist of a 0
stored in bit 7 and a 1 stored in bit 39. When storing a ternary
X, 0 is written to both bits in the pair.
Using bit pairs that are 32 bits apart simplifies the
computation of the pair by a processor. Assume that the
ternary value we wish to store is contained in two 32-bit
processor words. Word A contains the value to be stored and
word M contains a mask value, with a 0 in each position at
which an X is to be stored. The value to be written to bits
31-0 of the MH2080 is (A&M) and the value to be written to
bits 63-32 of the MH2080 is (~A&M).
A special instruction, CMPT DQ, performs the ternary
comparison processing for IPv4 CIDR addresses. The data on
the DQ bus are used directly as both the comparand and
compare mask bits 31-0, and the one's complement of the DQ
2
array. As a result of the comparison, the MH2080
generates an index that is used to access an external RAM
where port mapping data and other associated information
is stored.
A set of control states provides a powerful and flexible
control interface to the MH2080. This control structure
allows memory read and write, register read and write,
data move, comparison, validity control, addressing
control, and initialization operations.
The MH2080 architecture uses direct hardware control of
the device and an independent bus for returning match
results. Software control is also supported for systems
where maximum performance is not needed.
bus data are used as both the comparand and compare mask
bits 63-32. As a result, this instruction matches a DQ bit of 0
with bit pairs storing both 0 and X, and a DQ bit of 1 matches
bit pairs storing both 1 and X.
IPv4 CIDR addresses are prioritized by placing their
ternary-encoded values into the MH2080 memory such that
entries with longer netmasks (longer matches) have higher
priority (lower indices). Thus, when the MH2080 performs a
ternary comparison, it will return the index of the longest
matching entry. Typically, the system is initialized by a
processor that writes routing table information into the
MH2080. The index at which a write takes place is driven
onto the PA:AA bus, so that output port data can be written
simultaneously into the external RAM at the correct index.
The validity of a location in the Address Database is
determined by an extra bit called the Validity bit. This bit is
set and reset either with an index or an associative match.
Therefore, when a new entry is written to the database, its
Validity bit is set valid.
When a database location is deleted, the Validity bit for that
entry is reset, and the index of the location is driven onto the
Active Address bus. This simple mechanism allows easy
maintenance of the tables in both the database and the
external RAM.
The MH2080 supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the slight
timing overhead associated with the daisy chain is
unacceptable, the MH2080 is designed to facilitate external
prioritization across multiple devices.
For layer 2 applications, the MAC addresses are processed in
a binary mode, and the MH2080 looks for an exact match. An
MH2080 can be used to process both MAC addresses and
IPv4 CIDR in the same device.
Rev. 1.1a