mh2080 Music Semiconductors, Inc., mh2080 Datasheet - Page 30

• Manufacturer Part Number: mh2080
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

SWITCHING CHARACTERISTICS
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. With output and I/O pins unloaded.
11.
No.
1a
1b
2a
2b
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
3
4
5
6
7
8
9
-1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 7 on page 29).
Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts.
Applies to all cycle types except Compare cycles and Memory Read cycles (memory to DQ).
Applies to Compare cycle (including NEXT).
Control signals are /CS1, /CS2, /W, /AV, DSC, and the AC bus.
With load specified in Figure 6 on page 29, Test Load A from Table 7.
With load specified in Figure 6 on page 29, Test Load B from Table 7.
/E should be HIGH during /RESET active to ensure proper device defaults.
Test inputs are TDI and TMS signals.
Pins with internal pull-ups are /RESET, TCLK, TMS, TDI, and /TRST.
Symbol
tELEL
tELEL
tELEH
tELEH
tEHEL
tCVEL
tELCX
tELQX
tELQV
tEHQZ
tDVEL
tELDX
tFIVEL
tFIVFFV
tEHFFV
tEHQX
tEHQV
tMIVEL
tEHMX
tEHMV
tELMV
tMIVMV
tOEHQZ
tOELQV
tMIVOEL
tFIVOEL
tEHRSTL
tRSTLRSTH
tRSTHEL
tTIVTCLKH
tTCLKHTIX
tTCLKLTDOX
tTCLKLTDOV
tTCLKLTDOZ
Parameter
Chip Enable Cycle Time (Other Cycles)
Chip Enable Cycle Time (Compare Cycles)
Chip Enable LOW Pulse Width (Other Cycles)
Chip Enable LOW Pulse Width (Compare Cycles)
Chip Enable HIGH Pulse Width
Control Input to Chip Enable LOW Setup Time
Control Input to Chip Enable LOW HoldTime
Chip Enable LOW to Outputs Active
Chip Enable LOW to Outputs Valid
Chip Enable HIGH to Outputs High-Z
Data to Chip Enable LOW Setup Time
Data from Chip Enable LOW Hold Time
Full In Valid to Chip Enable LOW Setup Time
Full In Valid to Full Flag Valid
Chip Enable HIGH to Full Flag Valid
Chip Enable HIGH to Output Change
Chip Enable HIGH to Output Valid
Match In Valid to Chip Enable Low Setup Time
Chip Enable HIGH to Match Flag Change
Chip Enable HIGH to Match Flag Valid
Chip Enable LOW to Match Flag Valid
Match In Valid to Match Flag Valid
Output Enable HIGH to Outputs High-Z
Output Enable HIGH to Match Addess Outputs Valid
Match In Valid to Output Enable LOW
Full In Valid to Output Enable LOW
Chip Enable HIGH to Reset LOW
Reset Pulse Width
Reset HIGH to Chip Enable LOW
Test Input Valid to TCLK HIGH Setup Time
TCLK HIGH to Test Input Hold Time
TCLK LOW to TDI Change
TCLK LOW to TDO Valid
TCLK LOW to TDO High-Z
30
Register
Memory
/MM
/MM
/MF
/MF
Min
40
35
30
25
10
25
10
20
20
20
9
5
4
5
2
4
4
0
2
4
2
2
3
3
2
Max
10
15
30
35
15
12
15
42
10
10
20
5
5
7
8
units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3
4
3
4
5
5
6
6
7
6
8
9
9
Rev. 1.1a