am49pdl127ah Meet Spansion Inc., am49pdl127ah Datasheet - Page 14
![no-image](/images/no-image-200.jpg)
am49pdl127ah
Manufacturer Part Number
am49pdl127ah
Description
Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 16 Mbit 1m ? 16-bit Cmos Pseudo Static Ram
Manufacturer
Meet Spansion Inc.
Datasheet
1.AM49PDL127AH.pdf
(82 pages)
- Current page: 14 of 82
- Download datasheet (2Mb)
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
12
Am49PDL127AH61I
Am49PDL127AH70I
Am49PDL129AH61I
Am49PDL129AH70I
Am49PDL12
Order Number
Valid Combinations
7
Valid Combinations
A
T, S
T, S
T, S
T, S
H
AMD DEVICE NUMBER/DESCRIPTION
Am49PDL127AH/Am49PDL129AH
Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16
Mbit (1 M x 16-Bit) Pseudo Static RAM
A D V A N C E
61
Package Marking
M49000002J
M49000002I
M4900000K
M4900000L
I
Am49PDL127AH/Am49PDL129AH
T
TAPE AND REEL
T
S
TEMPERATURE RANGE
I
SPEED OPTION
See “Product Selector Guide” on page 5.
PROCESS TECHNOLOGY
H
PSEUDO SRAM DEVICE DENSITY
A
CONTROL PINS
7
9
I N F O R M A T I O N
=
=
=
=
=
=
=
7 inches
13 inches
Industrial (–40
0.13 µm
16 Mbits
1 CE Flash
2 CE Flash
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
°
C to +85
°
C)
December 18, 2003
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