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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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... SUPPLEMENT Am49LV128BM Stacked Multi-Chip Package (MCP) 128 Megabit ( 16-Bit) MirrorBit™ Uniform Sector Flash Memory and 32 Mbit ( 16-Bit) pseudo-static RAM with Page Mode DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single power supply operation — 3 volt read, erase, and program operations Manufactured on 0.23 µm MirrorBit process technology SecSi™ ...
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... MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit Product Informa- and Intel StrataFlash Memory Devices → Technical Docu- Migrating from Single-byte to Three-byte Device IDs Am49LV128BM June 17, 2004 ...
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... Erase And Programming Performance BGA Package Capacitance Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Function Truth Table . . . . . . . . . . . . . . . . . . . . . . . 55 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Recommended Operating Conditions . . . . . . . . . 57 pSRAM DC Characteristics . . . . . . . . . . . . . . . . . . 58 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . . 59 Read Operation . . . . . . . . . . . . . . . . . . . 59 Write Operation . . . . . . . . . . . . . . . . . . 60 Power Down Parameters . . . . . . . . . . . . 61 Other Timing Parameters . . . . . . . . . . . . 61 AC Test Conditions . . . . . . . . . . . . . . . . . 62 AC Measurement Output Load Circuit . . . . . . 62 Timing Diagrams Am49LV128BM 3 ...
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... Read/Write Timing #3 (OE#, WE#, LB#, UB# Control Power-up Timing # Power-up Timing # Power-down Entry and Exit Timing Standby Entry Timing after Read or Write . . . 74 AM49LV128BM MCP With Second PSRAM Supplier pSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . 76 Absolute Maximum Ratings (Note .76 4 Operating Characteristics (Over Specified Temperature Range Output Load Circuit ...
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... A0 to A19 A20 to A0 LB#ps UB#ps WE# OE# CE1#ps CE2ps June 17, 2004 = 2.7–3.1 V RY/BY# 128 M Bit Flash Memory DQ15 to DQ0 V s CCQ SS SSQ 32 M Bit DQ15 to DQ0 pseudo Static RAM Am49LV128BM Am49LV128BM Flash pSRAM 15 11 15, 11 105 110 65 105 110 DQ15 to DQ0 5 ...
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... DQ12 DQ8 DQ2 DQ11 NC DQ5 and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am49LV128BM A10 NC C8 A11 D8 D9 A15 A12 E8 E9 A13 A21 F8 F9 A14 A22 G8 G9 ...
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... RFU’s, and not connect them to any other signal. In case of any further inquiries about the above look- ahead pinout, please refer to the application note on this subject, or contact the appropriate AMD or Fujitsu sales office. Am49LV128BM A10 NC B10 NC Pseudo ...
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... pSRAM Power Supply Device Ground Pin Not Connected Internally UB#s = Upper Byte Control (pSRAM) LB#s = Lower Byte Control (pSRAM) RY/BY# = Ready/Busy Output 8 LOGIC SYMBOL 23 A22–21 A20–A0 DQ15–DQ0 CE1#ps CE2ps OE# WE# WP#/ACC RESET#f UB#s LB#s Am49LV128BM 16 RY/BY# June 17, 2004 ...
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... TEMPERATURE RANGE N = Light Industrial (–25 SPEED OPTION See Product Selector Guide and Valid Combinations WP# PROTECTION H = High sector protection L = Low sector protection pSRAM Blank= Standard Supplier a = Second Supplier PROCESS TECHNOLOGY M = 0.23 µm MirrorBit pSRAM DEVICE DENSITY Mbits Am49LV128BM ° ° + ...
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... See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing spec- ifications and to Figure 14 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Am49LV128BM DQ0– Addresses DQ7 ACC ...
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... CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. Am49LV128BM on this pin, the device auto ± 0.3 V. ...
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... Am49LV128BM power-up CC power sequence until CC is permitted output from the device IH 16-bit Sector Size Address Range (Kwords) (in hexadecimal) 32 000000–007FFF 32 008000–00FFFF 32 010000–017FFF 32 018000–01FFFF 32 020000–027FFF 32 028000–02FFFF 32 030000– ...
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... Am49LV128BM 16-bit Sector Size Address Range (Kwords) (in hexadecimal) 32 0E8000–0EFFFF 32 0F0000–0F7FFF 32 0F8000–0FFFFF 32 100000–107FFF 32 108000–10FFFF 32 110000–117FFF 32 118000–11FFFF 32 120000–127FFF 32 128000–12FFFF 32 130000–137FFF 32 138000– ...
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... Am49LV128BM 16-bit Sector Size Address Range (Kwords) (in hexadecimal) 32 268000–26FFFF 32 270000–277FFF 32 278000–27FFFF 32 280000–287FFF 32 288000–28FFFF 32 290000–297FFF 32 298000–29FFFF 32 2A0000–2A7FFF 32 2A8000–2AFFFF 32 2B0000–2B7FFF 32 2B8000– ...
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... Am49LV128BM 16-bit Sector Size Address Range (Kwords) (in hexadecimal) 32 3E8000–3EFFFF 32 3F0000–3F7FFF 32 3F8000–3FFFFF 32 400000–407FFF 32 408000–40FFFF 32 410000–417FFF 32 418000–41FFFF 32 420000–427FFF 32 428000–42FFFF 32 430000–437FFF 32 438000– ...
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... Am49LV128BM 16-bit Sector Size Address Range (Kwords) (in hexadecimal) 32 568000–56FFFF 32 570000–577FFF 32 578000–57FFFF 32 580000–587FFF 32 588000–58FFFF 32 590000–597FFF 32 598000–59FFFF 32 5A0000–5A7FFF 32 5A8000–5AFFFF 32 5B0000–5B7FFF 32 5B8000– ...
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... SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” Thus, the SecSi Sector Indicator Bit prevents cus- tomer-lockable devices from being used to replace de- vices that are factory locked. Note that the ACC Am49LV128BM 16-bit Sector Size Address Range (Kwords) ...
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... Flash Factory Locked). The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Note: MCP devices with second supplier pSRAM have 000000h address programmed to 0000h data. Am49LV128BM This IH ID June 17, 2004 ...
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... SA236–SA239 001011xx SA240–SA243 001100xx SA244–SA247 001101xx SA248–SA251 001110xx SA252 001111xx SA253 010000xx SA254 010001xx SA255 010010xx 010011xx Am49LV128BM A22–A15 010100xx 010101xx 010110xx 010111xx 011000xx 011001xx 011010xx 011011xx 011100xx 011101xx 011110xx 011111xx 100000xx 100001xx 100010xx 100011xx ...
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... Temporary Sector Group Unprotect Completed Notes: 1. All protected sector groups unprotected (If WP the last sector group will remain protected). 2. All previously protected sector groups are protected once again. Figure 1. Temporary Sector Group Unprotect Operation Am49LV128BM START ID (Note 1) IH (Note June 17, 2004 ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am49LV128BM START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
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... Table 5. CFI Query Identification String Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Am49LV128BM . LKO or WE initiate a write cycle, IH ...
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... Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to CFI publication 100) Erase Block Region 3 Information (refer to CFI publication 100) Erase Block Region 4 Information (refer to CFI publication 100) Am49LV128BM N µs N µ s (00h = not supported) ...
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... The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase- Am49LV128BM June 17, 2004 ...
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... Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 9 show the address and data requirements for the word program com- mand sequence. Am49LV128BM 25 ...
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... The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: Am49LV128BM –A . All subsequent ad- MAX 4 June 17, 2004 ...
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... WP# has an internal pullup; when unconnected, WP Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Am49LV128BM for opera ...
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... Yes No 4. Yes Yes No PASS Am49LV128BM When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. Therefore, DQ7 should be verified. DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “ ...
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... Write-to-Buffer Sequence in Progress Write address/data Wait 15 µs Read data as No Write address/data Device reverts to operation prior to Program Suspend Am49LV128BM Write Program Suspend Command Sequence XXXh/B0h Command is also valid for Erase-suspended-program operations Autoselect and SecSi Sector read operations are also allowed required ...
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... Figure 6 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Am49LV128BM June 17, 2004 ...
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... There is no time-out limit for the Erase Suspend com- mand. After the Erase Suspend command is written, the device will stay in Erase Suspend mode until the Erase Resume command or the RESET command/op- eration is written. Am49LV128BM 31 ...
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... The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume command is valid only during the Erase Suspend mode. 18. Command is valid when device is ready to read array data or when device is in autoselect mode. Am49LV128BM Fourth Fifth Sixth Addr Data Addr ...
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... DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 7. Data# Polling Algorithm DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com- plete, or whether the device has entered the Erase Am49LV128BM Yes Yes PASS 33 ...
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... Figure 9 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. Figure 21 shows the toggle bit timing dia- gram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Am49LV128BM No No Program/Erase Operation Complete ...
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... DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort- Reset command sequence to return the device to reading array data. See Write Buffer Programming section for more details. Am49LV128BM 35 ...
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... DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation. 36 Table 10. Write Operation Status DQ7 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle Invalid (not allowed toggle DQ7# Toggle DQ7# Toggle DQ7# Toggle Am49LV128BM DQ5 DQ2 DQ3 (Note 2) DQ1 0 N/A No toggle Toggle N/A Data 0 N/A Toggle N/A Data ...
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... Note: Operating ranges define those limits between which the functionality of the device is guaranteed. June 17, 2004 +0.8 V –0.5 V –2.0 V Figure +0 –2.0 V for SS Figure 10. Am49LV128BM Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform 37 ...
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... Automatic sleep mode enables the low power mode when addresses remain stable for < maximum Maximum max voltage requirements voltage requirements Not 100% tested. Am49LV128BM Min Typ Max ±1 ±1.0 5 MHz MHz ...
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... Note < INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level . IO Figure 12. Input Waveforms and Measurement Levels Am49LV128BM All Speeds Unit 1 TTL gate 0.0–3.0 1.5 0 the reference level is 0 ...
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... AC CHARACTERISTICS V Power-up CC Parameter Description t V Setup Time VCS CC t RESET# Low Hold Time RSTH V CC RESET# 40 Test Setup Min Min t VCS t RSTH Figure 13. V Power-up Diagram CC Am49LV128BM Speed Unit 50 µs 50 µs June 17, 2004 ...
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... Read Toggle and Data# Polling = V . Contact AMD for information on AC operations with Addresses Stable t ACC OEH t CE HIGH Z Figure 14. Read Operations Timings Am49LV128BM 15 11 Min 105 110 Max 105 110 IL Max 105 110 Max 25 30 Max 25 30 Max ...
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... AC CHARACTERISTICS A22-A2 A1-A0 Data Bus CE# OE# 42 Same Page PACC PACC t ACC Qa Qb Figure 15. Page Read Timings Am49LV128BM PACC Qc Qd June 17, 2004 ...
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... Note: Not 100% tested. CE#, OE# RESET# CE#, OE# RESET# June 17, 2004 Description Max Max Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t RP Figure 16. Reset Timings Am49LV128BM Unit 20 µs 500 ns 500 µs 43 ...
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... Min Min Min Min Min Min Min Min Min Min Min Min Typ Per Word Typ Per Word Typ Word Typ Word Typ Typ Min Min Am49LV128BM 11 Unit 110 ...
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... Figure 18. Accelerated Program Timing Diagram June 17, 2004 WPH A0h is the true data at the program address. OUT Figure 17. Program Operation Timings Am49LV128BM Read Status Data (last two cycles WHWH1 Status D OUT VHH 45 ...
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... SA = sector address (for Sector Erase Valid Address for reading status data (see “Write Operation Status”. 2. These waveforms are for the word mode. Figure 19. Chip/Sector Erase Operation Timings 555h for chip erase WPH t DH 55h 30h 10 for Chip Erase Am49LV128BM Read Status Data WHWH2 In Complete Progress June 17, 2004 ...
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... Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Data# Polling Timings (During Embedded Algorithms) June 17, 2004 Complement Complement Status Data Status Data Am49LV128BM VA High Z True Valid Data High Z Valid Data True 47 ...
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... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 22. DQ2 vs. DQ6 Am49LV128BM Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read June 17, 2004 ...
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... RSP Unprotect Note: Not 100% tested RESET VIDR CE# WE# Figure 23. Temporary Sector Group Unprotect Timing Diagram June 17, 2004 Min Min Program or Erase Command Sequence t RSP Am49LV128BM Unit 500 ns 4 µ VIDR 49 ...
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... For sector group protect For sector group unprotect Figure 24. Sector Group Protect and Unprotect Timing Diagram 50 Valid* Valid* Verify 60h 40h Sector Group Protect: 150 µs, Sector Group Unprotect Am49LV128BM Valid* Status June 17, 2004 ...
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... Effective write buffer specification is based upon a 16-word write buffer operation. June 17, 2004 Min Min Min Min Min Min Min Min Min Min Typ Per Word Typ Per Word Typ Word Typ Word Typ Typ Am49LV128BM 15, 11 Unit ...
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... BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Operation Timings Min –1.0 V –1.0 V –100 mA = 3.0 V, one pin at a time. CC Am49LV128BM PA DQ7# D OUT Max 12 1 +100 mA June 17, 2004 ...
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... V, 100,000 cycles. CC Test Setup OUT Test Conditions Am49LV128BM Unit Comments sec Excludes 00h programming prior to erasure (Note 5) sec µs µs Excludes system level µs overhead (Note 6) µs sec , 100,000 cycles. Additionally, CC Typ Max Unit FBGA 4 ...
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... AM49LV128BM MCP WITH STANDARD SUPPLIER PSRAM BLOCK DIAGRAM A20 ADDRESS LATCH & to BUFFER A0 DQ16 to INPUT / DQ9 OUTPUT DQ8 BUFFER to DQ1 POWER CE2 CONTROL CE1 MEMORY ROW CELL DECODER ARRAY 33,554,432 bit INPUT DATA SENSE / LATCH & SWITCH ...
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... L H (Note OE# can be VIL during Write operation if the following conditions are satisfied; Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is satisfied, OE stays during Write cycle. Am49LV128BM LB# UB# A20-0 DQ7-0 DQ15 ...
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... So, it should perform this program prior to regular read/write operation if Partial mode is used. Address Key The address key has the following format. Data Mode Sleep (default) RDa 8M Partial RDa Don’t Care (X) Am49LV128BM Address Data Write 1FFFFFh X Read Address Key Read Data (RDb) Address A20 A19 ...
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... Minimum DC voltage on input or I/O pins are -0.3 V. During voltage transitions, inputs may negative overshoot V 5 ns. June 17, 2004 Symbol 0.2 V. During voltage transitions, inputs may positive overshoot Am49LV128BM Min. Max. Unit 2.7 3 0.2 and DD 0 ≤+3.6 0 ...
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... IL minimum CE1 and CE2 = OUT max CE1 mA min. IH OUT PRC Am49LV128BM Min. Max. Unit µA -1.0 +1.0 µA -1.0 +1.0 2.4 – V – 0.4 V – 10 µA µA – 50 – 1.5 mA – 0.2 V, – 80 µ – ...
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... Low, CE1# must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. 8. Applicable when at least two of address inputs among applicable are switched from previous state (min) and t (min) must be satisfied. RC PRC Am49LV128BM Value Min. Max. Unit 65 1000 ns – ...
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... High Absolute minimum values and defined at minimum V level. 10. If the actual value of t WHOL minimum values, the actual t become longer by the amount of subtracting the actual value from the specified minimum value. Am49LV128BM Value Min. Max. Unit 65 1000 ns 0 – ...
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... Applicable when 8M Partial mode is programmed. Symbol t CHOX t CHWX t C2LH t CHH The Input Transition Time (t shown in AC Test Conditions below... If actual t than 5ns, it may violate AC specification of some timing parameters. Am49LV128BM Value Min. Max. Unit 10 – – ns 300 – s µ 1 – ...
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... Input Low Level IL V Input Timing Measurement Level REF t Input Transition Time 0 Figure 26. AC Measurement Output Load Circuit 62 Test Setup Between V and DEVICE UNDER OUT TEST 50pF Am49LV128BM 15, 11 Unit June 17, 2004 ...
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... CE1# OE UB# DQ (Output) Note: CE2 and WE# must be High for entire read cycle. Figure 27. Read TIming #1 (Basic Timing) June 17, 2004 t RC ADDRESS VALID BLZ t OLZ t CLZ VALID DATA OUTPUT Am49LV128BM t t CHAH ASC CHZ t OHZ t BHZ ...
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... OE UB# DQ (Output) Note: CE2 and WE# must be High for entire read cycle. Figure 28. Read Timing #2 (OE# and Address Access OLZ OH VALID DATA OUTPUT Am49LV128BM t RC ADDRESS VALID OHAH t OHZ t OH VALID DATA OUTPUT June 17, 2004 ...
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... VALID DATA OUTPUT t RC ADDRESS VALID PRC PRC ADDRESS ADDRESS VALID VALID t t PAA PAA VALID DATA OUTPUT VALID DATA OUTPUT (Normal Access) Am49LV128BM BHZ t t BLZ OH VALID DATA t BHZ OUTPUT PRC ADDRESS VALID t PAA t CHAH ...
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... Figure 31. Read Timing #5 (Random and Page Address Access ADDRESS VALID t t PRC RC ADDRESS ADDRESS VALID VALID t t PAA VALID DATA OUTPUT (Normal Access) Am49LV128BM PRC ADDRESS VALID t PAA VALID DATA OUTPUT (Page Access) June 17, 2004 ...
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... WC ADDRESS VALID VALID DATA INPUT t WC ADDRESS VALID ADDRESS VALID VALID DATA INPUT Am49LV128BM VALID DATA INPUT 67 ...
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... Note: CE2 must be High for Write Cycle. Figure 34. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control ADDRESS VALID VALID DATA INPUT Am49LV128BM t WC ADDRESS VALID VALID DATA INPUT June 17, 2004 ...
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... Note: CE2 must be High for Write Cycle. Figure 35. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control) June 17, 2004 t WC ADDRESS VALID VALID DATA INPUT Am49LV128BM t WC ADDRESS VALID VALID DATA INPUT 69 ...
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... WC ADDRESS VALID BWO VALID DATA INPUT VALID DATA INPUT Am49LV128BM VALID DATA INPUT t WC ADDRESS VALID VALID DATA INPUT t BWO ...
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... WRITE ADDRESS t WRC t ASC CLZ WRITE DATA INPUT t WC WRITE ADDRESS ASC WRITE DATA INPUT Am49LV128BM t RC READ ADDRESS t CHAH READ ADDRESS t CHAH OLZ OH READ DATA OUTPUT 71 ...
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... DS DH OLZ WRITE DATA INPUT t WC WRITE ADDRESS READ ADDRESS ASO BLZ WRITE DATA INPUT Am49LV128BM OHAH OHZ t OH READ DATA OUTPUT OHAH BHZ t OH READ DATA OUTPUT June 17, 2004 ...
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... V reaches specified minimum level. C2LH DD CE1# CE2 Note: The t specifies after V reaches specified minimum level and applicable to both CE1# and CE2. CHH DD June 17, 2004 t CHS t C2LH V min DD Figure 42. Power-up Timing #1 t CHH min DD Figure 43. Power-up Timing #2 Am49LV128BM t CHH 73 ...
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... Standby mode. If either of timing is not satisfied, it takes t CHOX CHWX period for standby mode from CE1# Low to High transition. Figure 45. Standby Entry Timing after Read or Write 74 t CHS t C2LP High-Z Power Down Mode Power Down Exit t CHWX Standby Active (Write) Am49LV128BM CHH CHHP Standby (min) RC June 17, 2004 ...
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... After t following Cycle #6, the Power Down Program is completed and returned to the normal operation. CP June 17, 2004 MSB* MSB RDa RDa X Cycle #3 Cycle #4 Am49LV128BM MSB* Key RDb Cycle #5 Cycle #6 75 ...
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... AM49LV128BM MCP WITH SECOND PSRAM SUPPLIER PSRAM BLOCK DIAGRAM Note: ZZ# = CE2pS on MCP pin-out. FUNCTION TRUTH TABLE Mode CE# ZZ# Standby (Note 2) H Standby (Note 2) X Write L Read L Active L Deep Sleep X Note: 1. When UB# and LB# are in select mode (low), I/O affected as shown. When LB# only is in the select mode only I/O O are affected as shown ...
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... OUT V = 3.1V, V =CMOS levels SB1 Chip Disabled 3. This device assumes a standby mode if the chip is disabled (either CE# high or both UB# and LB# high). In order to achieve low standby current all inputs must be within 0.2V of either VCC or VSS. Am49LV128BM Typ Min (Note 1) Max Unit 2.7 3.0 3.1 V 2.7 3 ...
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... OUTPUT LOAD CIRCUIT 78 Am49LV128BM June 17, 2004 ...
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... LBW UBW t 50 20000 WP t 7.5 WEH WHZ PDW PDH 20000 PGMAX Am49LV128BM Units ...
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... TIMING OF READ CYCLE (CE Am49LV128BM June 17, 2004 ...
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... TIMING WAVEFORM OF READ CYCLE (WE#=V Address CE# OE# LB#,UB# Data Out June 17, 2004 ) IH Am49LV128BM 81 ...
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... TIMING WAVEFORM OF PAGE MODE READ CYCLE (WE Am49LV128BM June 17, 2004 ...
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... TIMING WAVEFORM OF WRITE CYCLE (WE# CONTROL) June 17, 2004 Am49LV128BM 83 ...
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... TIMING WAVEFORM OF WRITE CYCLE (CE# CONTROL) 84 Am49LV128BM June 17, 2004 ...
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... TIMING WAVEFORM FOR SUCCESSIVE WE# WRITE CYCLES June 17, 2004 Am49LV128BM 85 ...
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... PAR mode, the VA register must be reset using the previously defined procedures. The default state for the ZZ# register will be such that ZZ# low will put the device into PAR mode after 1µs and never initiate a deep sleep mode unless appropri- Am49LV128BM June 17, 2004 ...
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... Deep Sleep is entered by bringing ZZ# low. After 1 µs, if the VAR register corresponding not set to Deep Sleep Disabled, the device will enter Deep Sleep Mode. The device will remain in this mode as long as ZZ# re- mains low. Am49LV128BM 87 ...
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... VARIABLE ADDRESS REGISTER 88 Am49LV128BM June 17, 2004 ...
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... VARIABLE ADDRESS REGISTER (VAR) UPDATE TIMINGS June 17, 2004 Am49LV128BM 89 ...
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... DEEP SLEEP MODE - ENTRY/EXIT TIMINGS VAR UPDATE AND DEEP SLEEP TIMINGS Item PAR and RMS ZZ# low to WE# low Chip (CE#, UB#/LB#) deselect to ZZ# low Deep Sleep Mode Deep Sleep Recovery 90 Symbol Min Max Unit t 1000 ns zzwe cdzz zzmin t 200 ns r Am49LV128BM June 17, 2004 ...
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... One-quarter of die 000000h - 07FFFFh 512Kb One-half of die Full Die One-quarter of die 180000h - 1FFFFFh 512Kb One-half of die June 17, 2004 Address Space Size Density 8Mb 000000h - 0FFFFFh 1Mb x 16 16Mb 000000h-1FFFFFh 2Mbx16 32Mb 8Mb 100000h - 1FFFFFh 1Mb x 16 16Mb Am49LV128BM 91 ...
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... Full die One-quarter of die One-half of die 92 Address Space Size Density 000000h - 07FFFFh 512Kb x 16 8Mb 000000h - 0FFFFFh 1Mb x 16 16Mb 000000h - 1FFFFFh 2Mb x 16 32Mb 180000h - 1FFFFFh 512Kb x 16 8Mb 100000h - 1FFFFFh 1Mb x 16 16Mb Am49LV128BM June 17, 2004 ...
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... Array Partition 1/4 Array 0V Chip Disabled 85°C 1/2 Array A 8Mb Device 0V Chip Disabled 85°C 16Mb Device A VIN = VCC or 0V, Chip in ZZ# mode 85°C A Am49LV128BM Typ Max Unit 50 75 µ µ µA 93 ...
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... OUTER ROW 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am49LV128BM ...
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... Changed column head to Value, added t eter, changed min value of t Notes 8, 9, and 10. AC Characteristics Added Power Down Parameters and Other Timing Pa- rameters tables. AM49LV128BM MCP with Second PSRAM Supplier Removed Capacitance section. Partial Array Refresh (PAR) specification. AH Removed reference to two versions. ...
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... Condition” to Vcc=3.1V... Changed “Page Mode Operating Supply Current. - Test Condition” to Vcc=3.1V... Changed “Page Mode Operating Supply Current. - Max.” to 25.0 Changed “Maximum Standby Current - Test Condition” to Vcc=3.1V... Changed “Maximum Standby Current - Max.” to 120. Am49LV128BM June 17, 2004 ...