s72ns512pe0kfdgg Meet Spansion Inc., s72ns512pe0kfdgg Datasheet - Page 8

• Manufacturer Part Number: s72ns512pe0kfdgg
• Description: The S72ns Series Is A Product Line Of Stacked Products Mcps And Pops , And Consists Of Ns Family Multiplexed Flash Memory Die Ddr Dram
• Manufacturer: Meet Spansion Inc.

4.
8
Input/Output Descriptions
Note
Signal descriptions apply only to valid products offered in the S72NS-P product family.
Amax – A16
ADQ15 – ADQ0
F-CE#
F-OE#
F-WE#
F-VCC
F-VCCQ
F-VSS
F-RDY
F-CLK
F-AVD#
F-RST#
F-WP#
F-ACC
D-A12 – D-A0
D-DQ15 – D-DQ0
D-CLK
D-CE#
D-CKE
D-BA1 – BA0
D-RAS#
D-CAS#
D-UDQM – D-LDQM
D-WE#
D-VSS
D-VSSQ
D-VCCQ
D-VCC
D-UDQS
D-LDQS
D-CLK#
RFU
NC
DNU
Signal
Flash Address inputs
Flash multiplexed Address and Data
Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
Flash Write Enable input
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
Flash Ground
Flash ready output. Indicates the status of the Burst read. V
data valid.
Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the
address input and activates burst mode operation. After the initial word is output,
subsequent rising edges of CLK increment the internal address counter. CLK should
remain low during asynchronous access.
Flash Address Valid input. Indicates to device that the valid address is present on the
address inputs. V
causes starting address to be latched on rising edge of CLK. V
address inputs
Flash hardware reset input. V
Flash hardware write protect input. V
four outermost sectors
Flash accelerated input. At V
device in unlock bypass mode. At V
Should be at V
DRAM Address inputs.
DRAM Data input/output
DRAM System Clock
DRAM Chip Select
DRAM Clock Enable
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
DRAM Data Input Mask
DRAM Write Enable input
DRAM Ground
DRAM Input/Output Buffer ground
DRAM Input/Output Buffer power supply
DRAM device power supply
DRAM Upper Data Strobe, output with read data and input with write data
DRAM Lower Data Strobe, output with read data and input with write data
DDR Clock for negative edge of CLK
Reserved for Future Use
No Connect. Can be connected to ground or left floating.
Do Not Use. This signal must be left floating
S72NS-P MCP/PoP Memory System Solutions
D a t a
IH
for all other conditions.
IL
S h e e t
= for asynchronous mode, indicates valid address; for burst mode,
HH
IL
= device resets and returns to reading array data
, accelerates programming; automatically places
( A d v a n c e
IL
Description
IL
, disables all program and erase functions.
= disables program and erase functions in the
I n f o r m a t i o n )
OL
= data invalid. V
IH
= device ignores
S72NS-P_00_05 February 14, 2008
OH
=
Flash
X
X
X
X
X
X
X
X
X
X
X
X
DRAM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X