lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 19

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

:.l Read Array
Jpon initial device power-up
jowerdown
node. This operation
lead Array command.
eads until
nternal WSM has started
sck-bit
he Read Array
lperation
luspend
bray
poltage and m can be V,, or V,,.
,.2 Read Identifier
‘he identifier
Lead Identifier
ommand
‘igure 3 retrieve
onfigura tion and master lock configuration
‘able 5 for identifier
Nperation,
Lead Array
ommand
nd RP can be V,,
dentifier
an be read:
Block Lock Configuration
.Block is Unlocked
*Block is Locked
-Reserved for Future Use
Master Lock Configuration
SDevice is Unlocked
,Device is Locked
,Reserved
IOTE:
. X selects the specific block
code memory
to be read. See Figure’3
-
SHARP
command
configuration,
or Byte Write
Codes command,
unless the WSM is suspended
write,
functions
for Future Use
write
another
mode, the device defaults
code operation
command,
Table 5. Identifier
command
Command
read cycles from addresses
the manufacturer,
functions
map.
another
Codes
Codes Command
independently
command
code values).
is also initiated
or V,,.
The device remains
the device
Suspend
the Read
until the WSM completes
command.
a block erase, byte write
valid
independently
the following
is initiated
for the device
and after exit from deep
lock configuration
is written.
Following
Codes
command.
command.
will
of the VP, voltage
device,
To terminate
Identifier
Following
by writing
by writing
not recognize
to read array
via an Erase
information
enabled for
of the VP,
block lock
codes (see
The Read
the Read
Once
shown
identifier
Like
Codes
LRS13023
code
the
the
the
the
the
the
its
or
in
changes all block data to FFH). Block preconditioning,
erase sequence
outputs
The
analyzing
iZ
Rp can be V,, or V,,.
4.4 Clear Status Register
Status register
Status Register
failure
software
cumulatively
writing
The status
error occurre
To clear the status register,
command
of the applied
This command
byte write
4.5 Block Erase Command
Erase is executed
two-cycle
written,
command
and an address
erase, and verify
(invisible
The status register
complete
successfully.
Read
command,
from
is written.
the falling edge of OE or CE, whichever
command
“1”s by the WSM and can only be reset by the Clear
4.3 Read Status Register
block
the status
must toggle to V,, before further
CPU
the status register
Status
erase, byte write,
conditions
several
status register
followed
to reset these bits, several operations
to the system).
functions
(50H) is written.
suspend
status register
sequence
command.
and
The status register
all subsequent
register
register
can
It may be read at any time by writing
during
Register
erasing
bits SR.5, SR.4, SR.3, and SR.1 are set to
VP, Voltage.
bytes in sequence)
is not functional
command.
is written,
within
whether
detect
one block at a time and initiated
are handled
(see Table 7). By allowing
by an block
modes.
may be read to determine
may be polled
independently
latch.
the sequence.
requires
or locking
A block
data when
command.
the block
until another
block
bit SR.7.
Command
Command
or, lock-bit
read operations
These bits indicate
The Read
After
the
It functions
the device
the Clear
RP can be V,,
appropriate
.
contents
internally
erase
operation
during
erase
erase
the two-cycle
to be erased
read (see Figure 4).
multiple
may be performed.
After
of the VP, voltage.
to determine
configuration
reads to update
valid command
completion
Status
Status Register
independently
are latched
setup
block erase or
confirm.
occurs. OE or
automatically
by the WSM
writing
output
sequencing
completed
blocks
or V,,.
Register
(such as
various
when
is first
system
(erase
block
if an
This
data
by a
this
the
by
on
17
or
is
a