k4t56043qf Samsung Semiconductor, Inc., k4t56043qf Datasheet
k4t56043qf
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... F-die DDR2 SDRAM 256Mb F-die DDR2 SDRAM Specification Version 0.91 September 2003 Page Preliminary DDR2 SDRAM Rev. 0.91 (Sep. 2003) ...
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... F-die DDR2 SDRAM Contents 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pintout & Mechnical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Command Truth Table 3.1 Command truth table 3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions 3.3 DM Truth Table 4. Absolute Maximum Rating 5. AC & DC Operating Conditions & Specifications ...
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... F-die DDR2 SDRAM Revision History Version 0.9 (Sep. 2003) - Initial Release Version 0.91 (Sep. 2003) - Removed D4 speed bin(400 4-4-4) - Added operation temperature condition - Changed setup/hold time values(tlS/tDS, tIH/tDH) - Added notes for setup/hold time(tIS/tDS, tIH/tDH) - Changed in/output capacitance values - Added tREFI values by T (85°C/95°C) ...
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... Small Classification T : DDR2 SDRAM 4. Density & Refresh 56 : 256M 8K/64ms 5. Organization Bank Bank 7. Interface (VDD & VDDQ) Q: SSTL-18(1.8V, 1.8V) DDR2-533 4-4-4 DDR2-400 3-3-3 K4T56043QF-GCD5 K4T56043QF-GCCC K4T56043QF-GLD5 K4T56043QF-GLCC K4T56083QF-GCD5 K4T56083QF-GCCC K4T56083QF-GLD5 K4T56083QF-GLCC Version M : 1st Generation A : 2nd Generation B : 3rd Generation C : 4th Generation ...
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... F-die DDR2 SDRAM 1.Key Features Speed DDR2-667 CAS Latency 5 tRCD(min) 15 tRP(min) 15 tRC(min) 55 • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz f for 400Mb/sec/pin, 267MHz f CK • 4 Bank • Posted CAS • Programmable CAS Latency • Programmable Additive Latency and 4 • ...
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... F-die DDR2 SDRAM Description The 256Mb DDR2 SDRAM chip is organized as either 16Mbit banks or 8Mbit x 8 I/O x 4banks banks device. This synchronous device achieve high speed double-data-rate transfer rates 667Mb/sec/pin (DDR2-667) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver(OCD) impedance adjustment, (4) On Die Ter- mination ...
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... F-die DDR2 SDRAM 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package 1 VDD NC VDDQ NC VDDL NC VSS VDD Notes: B1, B9, D1 for x4 organization. Pins B3 has identical capacitance as pins B7. VDDL and VSSDL are power and ground for the DLL recommended that they are isolated on the device from VDD, VDDQ, VSS, and VSSQ ...
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... F-die DDR2 SDRAM x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & ...
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... F-die DDR2 SDRAM FBGA Package Dimension(x4/x8 60- ∅ 0.45± 0.05 ∅0 #A1 11.00 ± 0.10 6.40 0.80 1. 3.20 (5.50) (0.90) (1.80) 11.00 ± 0.10 Page Preliminary DDR2 SDRAM # A1 INDEX MARK (OPTIONAL) 0.35± 0.05 MAX.1.20 Rev. 0.91 (Sep. 2003) ...
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... Input Rank selection on systems with multiple Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM ODT Input signal for x4x8 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT ...
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... F-die DDR2 SDRAM 2.3 256Mb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 512Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 1Gb Configuration ...
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... H Power Down Exit L 1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock. 2. Bank addresses BA0, BA1, BA2 (BA) determine which bank operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter- rupted by a Write" ...
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... CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION ( result of COMMAND (N). ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM & DC Operating Conditions Recommended DC Operating Conditions (SSTL - 1.8) ...
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... F-die DDR2 SDRAM Operating Temperature Condition SYMBOL PARAMETER TOPER Operating Temperature Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. 2. The operation temperature range are the temperature where all DRAM specification will be supported. Input DC Logic Level Symbol Symbol Parameter Parameter V V ...
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... F-die DDR2 SDRAM DQS DQS Hold Setup Time Time V DDQ V min IH(ac region V min IH(dc) V REF V max IL(dc) V max IL(ac Setup Hold Delta TF Delta TR Vil(dc)max - Vil(ac)max Setup Slew Rate = Falling Signal Setup Delta TF Setup Slew Rate Vih(ac)min - Vih(dc)min ...
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... F-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V (ac) ac differential input voltage ID V (ac) ac differential cross point voltage specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and IN(DC) UDQS specifies the input differential voltage |V ...
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... F-die DDR2 SDRAM Input Signal Overshoot/Undershoot Specification AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT Parameter Maximum peak amplitude allowed for overshoot area (See Figure 1): Maximum peak amplitude allowed for undershoot area (See Figure 1): Maximum overshoot area above VDD (See Figure1) ...
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... F-die DDR2 SDRAM Power and ground clamps are implemented on the following input only pins: 1. BA0-BA2 2. A0-A15 3. RAS 4. CAS ODT 8. CKE V-I Characteristics for input only pins with clamps Voltage across Minimum Power clamp(V) Clamp Current (mA) 0.0 0 0.1 0 0.2 0 0.3 0 0.4 0 0.5 0 0.6 0 0.7 0 ...
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... F-die DDR2 SDRAM Output Buffer Levels Output AC Test Conditions Symbol Parameter V Minimum Required Output Pull-up under AC Test Load OH V Maximum Required Output Pull-down under AC Test Load OL V Output Timing Measurement Reference Level OTR 1. The VDDQ of the device under test is referenced. ...
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... F-die DDR2 SDRAM Note 6 : This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty ohm value (no calibration) can only be achieved if the OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions. ...
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... F-die DDR2 SDRAM Table 1. Full Strength Default Pulldown Driver Characteristics Voltage (V) Minimum (23.4 Ohms) 0.2 8.5 0.3 12.1 0.4 14.7 0.5 16.4 0.6 17.8 0.7 18.6 0.8 19.0 0.9 19.3 1.0 19.7 1.1 19.9 1.2 20.0 1.3 20.1 1.4 20.2 1.5 20.3 1.6 20.4 1.7 20.6 1.8 1.9 Figure 1. DDR2 Default Pulldown Characteristics for Full Strength Driver 120 100 0.2 0.4 0.3 Pulldow n Current (mA) Nominal Default Nominal Default Low (18 ohms) High (18 ohms) 11.3 11.8 16.5 16.8 21.2 22.1 25.0 27.6 28.3 32.4 30.9 36.9 33.0 40.9 34.5 44.6 35.5 47.7 36.1 50.4 36.6 52.6 36.9 54.2 37.1 55.9 37.4 57.1 37.6 58.4 37.7 59.6 37.9 60.9 0.6 0.8 1.0 1.2 1.4 0.5 0.7 0.9 1.1 1.3 VOUT to VSSQ (V) Page ...
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... F-die DDR2 SDRAM Table 2. Full Strength Default Pullup Driver Characteristics Voltage (V) Minimum (23.4 Ohms) 0.2 -8.5 0.3 -12.1 0.4 -14.7 0.5 -16.4 0.6 -17.8 0.7 -18.6 0.8 -19.0 0.9 -19.3 1.0 -19.7 1.1 -19.9 1.2 -20.0 1.3 -20.1 1.4 -20.2 1.5 -20.3 1.6 -20.4 1.7 -20.6 1.8 1.9 Figure 2. DDR2 Default Pullup Characteristics for Full Strength Output Driver 0 -20 -40 -60 -80 -100 -120 0.2 0.4 0.6 0.3 0.5 Pullup Current (mA) Nominal Default Nominal Default Low (18 ohms) High (18 ohms) -11.1 -11.8 -16.0 -17.0 -20.3 -22.2 -24.0 -27.5 -27.2 -32.4 -29.8 -36.9 -31.9 -40.8 -33.4 -44.5 -34.6 -47.7 -35.5 -50.4 -36.2 -52.5 -36.8 -54.2 -37.2 -55.9 -37.7 -57.1 -38.0 -58.4 -38.4 -59.6 -38.6 -60.8 0.8 1.0 1.2 1.4 0.7 0.9 1.1 1.3 1.5 VDDQ to VOUT (V) Page ...
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... IBIS models need to be adjusted to a wider range as a result of any system cali- bration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the cali Calibrated Pulldow n Current (mA) Nominal Low (18 ...
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... F-die DDR2 SDRAM bration procedure is used possible to cause the device to operate outside the bounds of the default device characteristics tables and figures. In such a situation, the timing parameters in the specification can- not be guaranteed solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can’ ...
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... F-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Sym- Proposed Conditions bol IDD0 Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; ...
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... F-die DDR2 SDRAM IDD4W Operating burst write current; All banks open, Continuous burst writes CL(IDD CK(IDD), t RAS = t RASmax(IDD RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Operating burst read current ...
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... F-die DDR2 SDRAM For purposes of IDD testing, the following parameters are to be utilized Parameter CL(IDD) t RCD(IDD) t RC(IDD) t RRD(IDD)-x4/x8 t RRD(IDD)-x16 t CK(IDD) t RASmin(IDD) t RP(IDD) t RFC(IDD)-512Mb Detailed IDD7 The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification. ...
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... F-die DDR2 SDRAM Input/Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Electrical Characteristics & AC Timing for DDR2-667/533/400 (0 ° ...
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... F-die DDR2 SDRAM DQ output access time from tAC CK/CK DQS output access time from tDQSCK CK/CK CK high-level width tCH CK low-level width tCL CK half period tHP Clock cycle time, CL=x tCK DQ and DM input hold time tDH DQ and DM input setup time tDS Control & Address input ...
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... F-die DDR2 SDRAM Read postamble tRPST Active to active command tRRD period for 1KB page size products Active to active command tRRD period for 2KB page size products CAS to CAS command delay tCCD Write recovery time tWR Auto precharge write tDAL recovery + precharge time ...
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... DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF ...
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... F-die DDR2 SDRAM resisor to insure proper operation. DQS/ DQS CK/CK CK DQS DQS/DQS DQS timings are for linear signal transitions. See System Derating for other signal transitions. 6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation ...
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... F-die DDR2 SDRAM 12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency 13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 14. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns ...
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... F-die DDR2 SDRAM signal and V for a falling signal applied to the device under test. IL(dc tIS 18. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. ...
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... F-die DDR2 SDRAM in section 3.2.9. 24. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 25. ODT turn off time min is when the device starts to turn off ODT resistance. ...