k4t56043qf Samsung Semiconductor, Inc., k4t56043qf Datasheet - Page 6

• Manufacturer Part Number: k4t56043qf
• Description: 256mb F-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

Preliminary
256Mb F-die DDR2 SDRAM
DDR2 SDRAM
Description
The 256Mb DDR2 SDRAM chip is organized as either 16Mbit x 4 I/O x 4 banks or 8Mbit x 8 I/O x 4banks
banks device. This synchronous device achieve high speed double-data-rate transfer rates of up to
667Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive
latency, (2) write latency = read latency -1, (3) Off-Chip Driver(OCD) impedance adjustment, (4) On Die Ter-
mination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A fourteen bit address
bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For
example, 256Mb(x4) device receive 13/11/2 addressing.
The 256Mb DDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 256Mb DDR2 devices are available in 60ball FBGAs(x4/8).
Note: The functionality described and the timing specifications included in this data sheet are for the DLL
Enabled mode of operation.
Rev. 0.91 (Sep. 2003)
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