k4h560838c Samsung Semiconductor, Inc., k4h560838c Datasheet - Page 14

• Manufacturer Part Number: k4h560838c
• Description: Ddr Sdram Specification Version 0.6
• Manufacturer: Samsung Semiconductor, Inc.

256Mb C-die(x4/8) DDR SDRAM
3.2 Basic Functionality
Command
3.2.1 Power-Up and Initialization Sequence
*1
Power up & Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.)
No power sequencing is specified during power up or power down given the following criteria:
•
•
•
• A minimum resistance of 42 ohms(22 ohm series resistor + 22 ohm parallel resistor 5% tolerance)
If the above criteria cannot be met by the system design, the following table must be adhered
to during power up:
5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
7. Issue precharge commands for all banks of the device.
*1 Sequence of 6 & 7 is regardless of the order.
limits the input current from the V
V
V
V
Voltage Description
VDDQ
VTT
VREF
"Low" to all of the rest address pins, A1~A11 and BA1)
- Apply V
- Apply V
DD
TT
REF
to lock the DLL. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0)
CK
CK
is limited to 1.44V (reflecting V
and V
ALL Banks
precharge
tracks V
0
DD
t
DD
DD
RP
Q are driven from a single power converter output, and
1
DD
Q before or at the same time as V
before or at the same time as V
Q/2, and
E M R S
2
2 Clock min.
3
DLL Reset
MRS
4
Sequencing
After or with VDD
After or with VDDQ
After or with VDDQ
2 Clock min.
TT
Figure 4. Power up and initialization sequence
5
DD
supply into any pin.
ALL Banks
precharge
Q(max)/2 + 50mV V
6
t
R P
7
1st Auto
Refresh
- 14 -
DD
8
TT
Q.
& Vref.
9
REF
Voltage Relationship to avoid latch-up
<VDD + 0.3V
< VDDQ +0.3V
<VDDQ +0.3V
t
10
RFC
variation +40m V V
11
min.200 Cycle
12
2nd Auto
Refresh
13
REV. 0.7 Jan. 31. 2002
TT
14
variation), and
t
RFC
15
16
Register Set
M o d e
17
2 Clock min.
18
C o m m a n d
Any
19