ic42s16101-7tig ETC-unknow, ic42s16101-7tig Datasheet - Page 30

• Manufacturer Part Number: ic42s16101-7tig
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16101
30
Precharge
The precharge command sets the bank selected by pin
A11 to the precharged state. This command can be
executed at a time t
command to the same bank. The selected bank goes to
the idle state at a time t
precharge command, and an active command can be
executed again for that bank.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time.
This input to pin A11 is ignored in the latter case.
CAS latency = 2, burst length = 4
CAS latency = 3, burst length = 4
COMMAND
COMMAND
CLK
CLK
I/O
I/O
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
RAS
READ A0
READ A0
following the execution of an active
RP
following the execution of the
PRECHARGE (BANK 0)
D
OUT
A0
D
D
PRE 0
PRE 0
OUT
OUT
A0
A1
PRECHARGE (BANK 0)
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
command to the completion of the burst output is the clock
cycle of CAS latency.
D
t
D
RQL
OUT
OUT
CAS
CAS
CAS Latency
CAS
CAS
A1
A2
t
t
RQL
RQL
RQL
D
OUT
) from the execution of the precharge
HI-Z
A2
Integrated Circuit Solution Inc.
HI-Z
3
3
DR025-0F 01/17/2005
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2