ic42s32200 ETC-unknow, ic42s32200 Datasheet - Page 22

• Manufacturer Part Number: ic42s32200
• Description: 512k X 32 Bit X 4 Banks 64-mbit Sdram
• Manufacturer: ETC-unknow

IC42S32200
IC42S32200L
Electrical Characteristics and Recommended A.C.Operating Conditions
22
Note:
1. Stress greater than those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of
4. These parameters depend on the output loading.Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
* CL is CAS# Latency.
RC
RRD
RCD
RP
RAS
CK2
CK3
AC2
AC3
OH
CH
CL
IS
IH
LZ
HZ
DAL
SRX
RFC
REF
WR
CCD
MRS
PDE
tCK and tRC.Input signals are changed one time during tCK.
(VDD =3.3V ± 0.3V,Ta =0~70 C)(Note:5,6,7,8)
Row cycle time
(same bank)
Row activate to row activate delay
(different banks)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
Row activate to precharge time
(same bank)
Clock cycle time
Access time from CLK
(positive edge)
Data output hold time
Clock high time
Clock low time
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Data output low impedance
Data output high impedance
Input data to active/refresh command
delay time (During Auto-precharge)
Exit self refresh and active command
Auto refresh Period
Refresh cycle time(4096)
Write Recovery Time
CAS# to CAS# Delay time
Mode Register Set cycle time
CKE to clock enable or power down exit
setup mode
A.C. Parameter
CL* = 2
CL* = 3
CL* = 2
CL* = 3
1.5/1.75/2
2CLK+t
12/14/16
60/70/80
18/21/24
18/21/24
42/49/56
2/2.5/2.5
60/70/80
- / - /10
6/7/8
2/3/3
2/3/3
Min.
70
1
1
2
1
2
1
RP
- 6/7/8
Integrated Circuit Solution Inc.
5.5/5.5/6
5.5/5.5/6
100,000
- / - /8
Max.
64
DR036-0D 02/04/2005
Unit
CLK
ms
ns
Note
10
10
10
10
9
9
9
9
9
9
9
9
8