ic42s32200 ETC-unknow, ic42s32200 Datasheet - Page 6

• Manufacturer Part Number: ic42s32200
• Description: 512k X 32 Bit X 4 Banks 64-mbit Sdram
• Manufacturer: ETC-unknow

IC42S32200
IC42S32200L
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth
table for the operation commands.
6
Note:
1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high
2. CKEn signal is input level when commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1,2,4,8,and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
6. DQM0-3
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and Auto Precharge Active
Read
Read and Autoprecharge
Mode Register
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Clock Suspend Mode Entry Active
Power Down Mode Entry
Clock Suspend Mode Exit Active
Power Down Mode Exit
Data Write/Output Enable Active
Data Mask/Output Disable Active
CKEn-1 signal is input level one clock cycle before the commands are provided.
When this command is asserted in the burst cycle,device state is clock suspend mode.
State
Idle
Any
Any
Active
Active
Active
Set Idle
Any
Active
Any
Idle
Idle
Idle
(SelfRefresh)
Any
Any
(PowerDown)
Table 2.Truth Table (Note (1),(2))
(5)
(3)
(4)
(3)
(3)
(3)
(3)
CKEn-1 CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
(6)
BS0,1
V
V
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
A10
Row address
L
H
L
H
L
H
OP code
X
X
X
X
X
X
X
X
X
X
X
X
Column
address
(A0 ~A7)
Column
address
(A0 ~A7)
A9-0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Integrated Circuit Solution Inc.
L
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
DR036-0D 02/04/2005
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X