m464s1724kus Samsung Semiconductor, Inc., m464s1724kus Datasheet - Page 12

• Manufacturer Part Number: m464s1724kus
• Description: Sdram Unbuffered Sodimm
• Manufacturer: Samsung Semiconductor, Inc.

15.0 SIMPLIFIED TRUTH TABLE
Note :
1. OP Code : Operand code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
128MB Unbuffered SODIMM
Register
Refresh
Bank active & row addr.
Read &
column address
Write &
column address
Burst stop
Precharge
Clock suspend or
active power down
Precharge power down mode
DQM
No operation command
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
A new command can be issued after 2 clock cycles of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Command
Mode register set
Auto refresh
Self
refresh
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
Bank selection
All banks
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKEn
X
H
H
X
X
X
X
X
H
H
X
L
L
L
12 of 13
CS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
WE
H
H
H
H
H
H
L
X
L
L
L
X
V
X
X
X
V
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
Rev. 1.2 August 2008
BA
V
V
V
V
X
0,1
A
OP code
10
Row address
H
H
H
L
L
L
/AP
X
X
X
X
X
X
X
A
address
address
Column
Column
0
SDRAM
A
~ A
X
11
9,
Note
1,2
4,5
4,5
3
3
3
3
4
4
6
7