m464s6453cks Samsung Semiconductor, Inc., m464s6453cks Datasheet - Page 11

• Manufacturer Part Number: m464s6453cks
• Description: Pc133/pc100 Sodimm
• Manufacturer: Samsung Semiconductor, Inc.

M464S6453CKS-L7A/L1H/L1L, C7A/C1H/C1L(Intel SPD 1.2B ver. based)
•Organization : 64MX64
•Composition : 64MX8 *8
•Used component part # : K4S510832C-L7A/C7A/L1H/C1H/L1L/C1L
•# of rows in module : 2 rows
•# of banks in component : 4 banks
•Feature : 1,200 mil height & double sided
•Refresh : 8K/64ms
•Contents :
M464S6453CKS
Byte
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
#
0
1
2
3
4
5
6
7
8
9
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Rows on this assembly
Data width of this assembly
...... Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time from clock @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuration type
Refresh rate & type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column address
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of banks on SDRAM device
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
SDRAM module attributes
SDRAM device attributes : General
SDRAM cycle time @CAS latency of 2
SDRAM access time @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time @CAS latency of 1
Minimum row precharge time (=t
Minimum row active to row active delay (t
Minimum RAS to CAS delay (=t
Minimum activate precharge time (=t
Module Row density
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Function described
RCD
RP
)
)
RAS
)
R R D
)
tered & redundant addressing
precharge all, auto precharge
Burst Read Single bit Write
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
7.8us, support self refresh
10ns
15ns
45ns
Non-buffered/Non-Regis-
+/- 10% voltage toleance,
-7A
6ns
Function Supported
1, 2, 4, 8 & full page
2 Rows of 256MB
256bytes (2K-bit)
t
CCD
Non parity
128bytes
SDRAM
4 banks
2 Rows
64 bits
LVTTL
0 CLK
0 CLK
None
10ns
10ns
20ns
20ns
20ns
50ns
2&3
-1H
6ns
6ns
2ns
1ns
2ns
13
10
x 8
= 1CLK
-
-
-
10ns
12ns
20ns
50ns
-1L
6ns
7ns
2ns
1ns
2ns
PC133/PC100 SODIMM
A0h
2Dh
-7A
75h
54h
60h
0Fh
15h
08h
15h
Hex value
Rev. 0.1 Feb. 2002
32ns
0Dh
-1H
80h
08h
04h
0Ah
02h
40h
00h
01h
A0h
60h
00h
82h
08h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
A0h
60h
00h
00h
14h
14h
14h
40h
20h
10h
20h
32ns
C0h
A0h
60h
70h
14h
20h
10h
20h
-1L
Note
1
1
2
2
2
2
2
2