m391b5273bh1 Samsung Semiconductor, Inc., m391b5273bh1 Datasheet - Page 29

• Manufacturer Part Number: m391b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Command and Address Timing
DLL locking time
internal READ Command to PRECHARGE Command
delay
Delay from start of internal write transaction to internal
read command
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK refer-
enced to V
Command and Address hold time from CK, CK refer-
enced to V
Command and Address setup time to CK, CK refer-
enced to V
Control & Address Input pulse width for each input
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
Exit Self Refresh to commands requiring a locked DLL
Minimum CKE low width for Self refresh entry to exit
timing
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
Unbuffered DIMM
IH
IH
IH
(AC) / V
(AC) / V
(AC) / V
IL
IL
IL
Parameter
(AC) levels
(AC) levels
(AC) levels
Speed
tDAL(min)
tIS(base)
tIH(base)
tIS(base)
Symbol
tZQoper
tCKESR
tCKSRE
tCKSRX
tXSDLL
tMPRR
tZQinitI
AC150
tZQCS
tDLLK
tWTR
tMRD
tMOD
tCCD
tRAS
tRRD
tRRD
tFAW
tFAW
tXPR
tRTP
tIPW
tWR
tXS
max(5nCK,tRFC +
tCKE(min) + 1tCK
max(5nCK, tRFC
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,10ns)
tDLLK(min)
max(5nCK,
max(5nCK,
125 + 150
+ 10ns)
10ns)
10ns)
10ns)
max
max
max
max
max
37.5
MIN
512
125
200
780
512
256
15
50
64
4
4
1
See 13.3 " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 37
DDR3-1066
29 of 33
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max(5nCK,tRFC +
tCKE(min) + 1tCK
max(5nCK, tRFC
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
WR + roundup (tRP / tCK(AVG))
(4nCK,7.5ns)
(4nCK,6ns)
tDLLK(min)
max(5nCK,
max(5nCK,
65+125
+ 10ns)
10ns)
10ns)
10ns)
MIN
max
max
max
max
max
512
140
620
512
256
15
30
45
65
64
4
4
1
DDR3-1333
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Rev. 1.0 December 2008
max(5nCK,tRFC +
tCKE(min) + 1tCK
max(5nCK, tRFC
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,6ns)
tDLLK(min)
max(5nCK,
max(5nCK,
TBD+125
+ 10ns)
10ns)
10ns)
10ns)
TBD
TBD
MIN
max
max
max
max
max
512
560
512
256
15
30
40
64
4
4
1
DDR3-1600
DDR3 SDRAM
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ns
ns
ps
ps
ps
ps
b,16,27
Note
e,18
b,16
b,16
22
28
23
e
e
e
e
e
e
e