m391b5273bh1 Samsung Semiconductor, Inc., m391b5273bh1 Datasheet - Page 9

• Manufacturer Part Number: m391b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

8.1 Address Mirroring Feature
There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The
length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To
extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.
The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical
support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5,
A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin
assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired
straight.
8.1.1 DRAM Pin Wiring for Mirroring
Figure 1 illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the DRAM pins, is obviously shorter. The via grid is smaller as well.
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limi-
tations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know
if the rank is mirrored or not. This requires a fewrules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a
requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mir-
rored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring
the address when accessing the second rank.
Unbuffered DIMM
Connector Pin
BA0
BA1
A3
A4
A5
A6
A7
A8
Figure 1 - Wiring Differences for Mirrored and Non-Mirrored Addresses
Rank 0
BA0
BA1
A3
A4
A5
A6
A7
A8
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DRAM Pin
Rev. 1.0 December 2008
Rank 1
BA1
BA0
A4
A3
A6
A5
A8
A7
DDR3 SDRAM