ppc405cr Applied Micro Circuits Corporation (AMCC), ppc405cr Datasheet - Page 8

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ppc405cr

Manufacturer Part Number
ppc405cr
Description
Powerpc 405cr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet

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PPC405CR – PowerPC 405CR Embedded Processor
UART
IIC Bus Interface
General Purpose IO (GPIO) Controller
8
- Buffered memory to peripheral transfers
Four channels
Scatter/Gather capability for programming multiple DMA operations
8-, 16-, 32-bit peripheral support (OPB and external)
32-bit addressing
Address increment or decrement
Internal 32-byte data buffering capability
Supports internal and external peripherals
Support for memory mapped peripherals
Support for peripherals running on slower frequency buses
One 8-pin UART and one 4-pin UART interface provided
Selectable internal or external serial clock to allow wide range of baud rates
Register compatibility with NS16550 register set
Complete status reporting capability
Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
Fully programmable serial-interface characteristics
Supports DMA using internal DMA engine
Compliant with Phillips® Semiconductors I
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed V
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocol
Programmable error recovery
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses.
All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabil-
ities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:
- 7 of 8 chip selects.
- All seven external interrupts.
- All nine instruction trace pins.
Each GPIO output is separately programmable to emulate an open-drain driver (two states, drive to zero or
open circuit).
DD
IIC interface
2
C Specification, dated 1995
Revision 1.02 – January 11, 2005
Data Sheet
AMCC

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