mc54hc165a Freescale Semiconductor, Inc, mc54hc165a Datasheet

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mc54hc165a

Manufacturer Part Number
mc54hc165a
Description
8-bit Serial Parallel-input/serial-output Shift Register
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High–Performance Silicon–Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
clock sources or by designating one of the clock inputs to act as a clock
inhibit.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
10/95
PARALLEL LOAD
Motorola, Inc. 1995
The MC54/74HC165A is identical in pinout to the LS165. The device
This device is an 8–bit shift register with complementary outputs from the
The 2–input NOR clock may be used either by combining two independent
CLOCK INHIBIT
PARALLEL
SERIAL SHIFT/
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
INPUTS
SERIAL
INPUT
DATA
DATA
CLOCK
S A
G
A
B
C
D
E
H
F
11
12
13
14
10
15
3
4
5
6
1
2
Parallel Load
X = don’t care
Serial Shift/
LOGIC DIAGRAM
H
H
H
H
H
H
H
L
Clock
H
X
L
L
X
L
Q An – Q Gn = Data shifted from the preceding stage
Inputs
9
7
Inhibit
Clock
X
H
X
L
L
L
Q H
Q H
PIN 16 = V CC
PIN 8 = GND
OUTPUTS
SERIAL
DATA
S A
X
H
H
X
X
X
L
L
FUNCTION TABLE
a
A – H
1
X
X
X
X
X
X
X
h
Internal Stages
Q A
H
H
a
L
L
No Change
No Change
Q An
Q An
Q An
Q An
Q B
REV 0
b
PARALLEL LOAD
MC54/74HC165A
SERIAL SHIFT/
16
16
16
16
1
Output
1
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Q Gn
Q Gn
Q Gn
Q Gn
Q H
CLOCK
ORDERING INFORMATION
h
1
1
GND
Q H
PIN ASSIGNMENT
G
E
H
F
Asynchronous Parallel Load
Serial Shift via Clock
Serial Shift via Clock Inhibit
Inhibited Clock
No Clock
1
2
3
4
5
6
7
8
CERAMIC PACKAGE
PLASTIC PACKAGE
TSSOP PACKAGE
Operation
Operation
SOIC PACKAGE
CASE 948F–01
CASE 751B–05
CASE 620–10
CASE 648–08
16
15
14
13
12
10
11
DT SUFFIX
9
N SUFFIX
D SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
TSSOP
V CC
CLOCK INHIBIT
D
C
B
A
S A
Q H

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mc54hc165a Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High–Performance Silicon–Gate CMOS The MC54/74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible ...

Page 2

MC54/74HC165A Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

DC ...

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MC54/74HC165A Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

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INPUTS (Pins 11, 12, 13, 14 Parallel Data inputs. Data on these inputs are asynchro- nously entered in parallel into the internal flip–flops when the Serial Shift/Parallel Load ...

Page 6

MC54/74HC165A CLOCK 90% 50% OR CLOCK INHIBIT 10 1/f max t PLH t PHL 90 50% 10% t TLH t THL Figure 1. Serial–Shift Mode t r 90% INPUT ...

Page 7

A SERIAL SHIFT/ 1 PARALLEL LOAD 10 SERIAL DATA INPUT CLOCK 2 CLOCK 15 INHIBIT CLOCK CLOCK INHIBIT S A SERIAL SHIFT/ PARALLEL LOAD PARALLEL D DATA E INPUTS F ...

Page 8

MC54/74HC165A –A – –T – SEATING PLANE 0.25 (0.010) M –A – 0.25 (0.010) –A – ...

Page 9

K 16X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 –V– C 0.10 (0.004) –T– SEATING D PLANE Motorola reserves the right to make changes without ...

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