adsst-21065lks-240 Analog Devices, Inc., adsst-21065lks-240 Datasheet
adsst-21065lks-240
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adsst-21065lks-240 Summary of contents
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... Algorithms Compatible Ports Interface to External SDRAM Melody and SHARC are registered trademarks of Analog Devices, Inc. DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater Systems, Inc. Dolby and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation. SRS is a registered trademark and Circle Surround trademark of SRS Labs. ...
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SST-Melody-SHARC–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Case Operating Temperature CASE V High Level Input Voltage IH V Low Level Input Voltage IL1 V Low Level Input Voltage IL2 NOTES 1 See Environmental Conditions section for information ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Case Temperature Part Number Range ADSST-21065LKS-240 0°C to 85°C ADSST-21065LCS-240 –40°C to +100°C ADSST-21065LKCA-240 0°C to 85°C ADSST-21065LKS-264 0° ...
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... CAS 43 SDWE 44 45 VDD DQM 46 SDCKE 47 SDA10 48 GND 49 DMAG1 50 DMAG2 51 HBG 52 208-LEAD MQFP PIN CONFIGURATIONS OO ADSST-21065L TOP VIEW (Not to Scale CONNECT –4– 156 VDD 155 GND 154 GND BMS 153 BSEL 152 151 TCK 150 GND 149 TMS 148 ...
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NC7 NC8 ADDR18 ADDR17 TCK GND ADDR23 ADDR21 RESET TDO BSEL ADDR22 EMU TRST TMS BMS FLAG4 ID1 TDI ID0 FLAG7 FLAG5 FLAG6 VDD DATA29 DATA30 DATA31 VDD DATA26 DATA27 DATA28 VDD DATA23 DATA25 DATA24 VDD ...
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SST-Melody-SHARC Pin No. Mnemonic Pin No RFS0 54 3 GND 55 4 RCLK0 56 5 DR0A 57 6 DR0B 58 7 TFS0 59 8 TCLK0 GND 62 11 DT0A ...
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Ball No. Mnemonic Ball No. Mnemonic A1 NC1 B1 DR0A A2 NC2 B2 RFS0 IRQ0 A3 FLAG2 B3 A4 ADDR0 B4 FLAG0 A5 ADDR3 B5 ADDR2 A6 ADDR6 B6 ADDR5 A7 ADDR7 B7 ADDR9 A8 ADDR8 B8 ADDR12 A9 ADDR11 ...
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SST-Melody-SHARC SST-Melody-SHARC pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or ...
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Mnemonic Type Function HBG Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control I/O of the external bus. HBG is asserted by the SST-Melody-SHARC until HBR is released multi- processor system, ...
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SST-Melody-SHARC Mnemonic Type Function TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan. TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor. TDI I/S ...
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GENERAL DESCRIPTION (continued from page 1) With 32-bit audio quality, the SST-Melody-SHARC audio processor auto-detects and decodes audio formats in real-time, enabling end users to enjoy a theater-quality audio experience in their homes. The solutions can be customized to meet ...
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SST-Melody-SHARC SOFTWARE ARCHITECTURE The audio DSP chipsets from Analog Devices allows designers to make value additions to product features working off the high end base functionality that they are provided with. The software has the following parts: SST-Melody-SHARC • Executive ...
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Independent, Parallel Computation Units The arithmetic/logic unit (ALU), multiplier, and shifter all perform single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit ...
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SST-Melody-SHARC Systems with several SDRAM devices connected in parallel may require buffering to meet overall system timing requirements. The SST-Melody-SHARC supports pipelining of the address and control signals to enable such buffering between itself and mul- tiple SDRAM devices. Host ...
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POWER DISSIPATION These specifications apply to the internal power portion of V supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see the technical note SHARC Power Dissipation Measurements. Specifications are ...
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SST-Melody-SHARC OUTPUT DRIVE CURRENT 80 V 3.6V, – 3.3V, + 3.1V, +100 C 0 –20 3.1V, +100 C –40 3.3V, +25 C –60 3.1V, +85 C – –100 –120 0 0.50 1.00 1.50 ...
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RISE TIME 4.0 3.0 2.0 1 100 120 LOAD CAPACITANCE – pF Figure 8. Typical Rise and Fall Time (0.8 V–2 –1 ...
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SST-Melody-SHARC The P equation is calculated for each class of pins that can drive: EXT Pin Type No. of Pins Address 11 MS0 1 SDWE 1 Data 32 SDRAM CLK 1 A typical power consumption can now be calculated for ...
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BSC SQ 1.70 MAX 3.60 3.40 3.20 0.50 0.08 (LEAD 0.25 COPLANARITY) VIEW A ROTATED 90 CCW REV. 0 OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-196) Dimensions shown in millimeters 1.00 BSC BALL PITCH TOP VIEW ...
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