adsst-21065lks-240 Analog Devices, Inc., adsst-21065lks-240 Datasheet - Page 14

• Manufacturer Part Number: adsst-21065lks-240
• Description: High End, Multichannel, 32-bit Floating-point Audio Processor
• Manufacturer: Analog Devices, Inc.

SST-Melody-SHARC
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements. The
SST-Melody-SHARC supports pipelining of the address and
control signals to enable such buffering between itself and mul-
tiple SDRAM devices.
Host Processor Interface
The SST-Melody-SHARC’s host interface provides easy con-
nection to standard microprocessor buses—8-, 16-, and
32-bit—requiring little additional hardware. Supporting asynchronous
transfers at speeds up to 1× clock frequency, the host interface is
accessed through the SST-Melody-SHARC’s external port. Two
channels of DMA are available for the host interface; code and
data transfers are accomplished with low software overhead.
The host processor requests the SST-Melody-SHARC’s external
bus with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
IOP registers of the SST-Melody-SHARC and can access the
DMA channel setup and mailbox registers. Vector interrupt
support enables efficient execution of host commands.
DMA Controller
The SST-Melody-SHARC’s on-chip DMA controller allows
zero-overhead, nonintrusive data transfers without processor
intervention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the SST-Melody-SHARC’s
internal memory and either external memory, external peripher-
als, or a host processor. DMA transfers can also occur between
the SST-Melody-SHARC’s internal memory and its serial ports.
DMA transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32-, or 48-
bit internal words is performed during DMA transfers.
Ten channels of DMA are available on the SST-Melody-SHARC—
eight via the serial ports, and two via the processor’s external
port (for either host processor, other SST-Melody-SHARC,
memory or I/O transfers). Programs can be downloaded to the
SST-Melody-SHARC using DMA transfers.
Asynchronous off-chip peripherals can control two DMA channels
using DMA Request/Grant lines (DMAR1–2, DMAG1–2).
Other DMA features include interrupt generation on completion of
DMA transfers and DMA chaining for automatically linked
DMA transfers.
Serial Ports
The SST-Melody-SHARC features two synchronous serial ports
that provide an inexpensive interface to a wide variety of digital
and mixed-signal peripheral devices. The serial ports can oper-
ate at 1× clock frequency, providing each with a maximum data
–14–
rate of 33 Mbit/s. Each serial port has a primary and a secondary
set of transmit and receive channels. Independent transmit and
receive functions provide greater flexibility for serial communi-
cations. Serial port data can be automatically transferred to and
from on-chip memory via DMA. Each of the serial ports supports
three operation modes: DSP serial port mode, I
commonly used by audio codecs), and TDM (Time Division
Multiplex) multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with selectable word lengths of three bits
to 32 bits. They offer selectable synchronization and transmit
modes and optional µ-law or A-law companding. Serial port
clocks and frame syncs can be internally or externally generated.
The serial ports also include keyword and keymask features to
enhance interprocessor communication.
Programmable Timers and General-Purpose I/O Ports
The SST-Melody-SHARC has two independent timer blocks, each
of which performs two functions—Pulsewidth Generation and
Pulse Count and Capture.
In Pulsewidth Generation mode, the SST-Melody-SHARC can
generate a modulated waveform with an arbitrary pulsewidth
within a maximum period of 71.5 secs.
In Pulse Counter mode, the SST-Melody-SHARC can measure
either the high or low pulsewidth and the period of an input
waveform.
The SST-Melody-SHARC also contains 12 programmable,
general-purpose I/O pins that can function as either input or
output. As output, these pins can signal peripheral devices; as
input, these pins can provide the test for conditional branching.
Program Booting
The internal memory of the SST-Melody-SHARC can be
booted at system power-up from an 8-bit EPROM, a host processor,
or external memory. Selection of the boot source is controlled by
the BMS (Boot Memory Select) and BSEL (EPROM Boot) pins.
Either 8-, 16-, or 32-bit host processors can be used for booting.
For details, see the descriptions of the BMS and BSEL pins in the
Pin Function Descriptions section.
Multiprocessing
The SST-Melody-SHARC offers powerful features tailored to
multiprocessing DSP systems. The unified address space allows
direct interprocessor accesses of both SST-Melody-SHARC’s IOP
registers. Distributed bus arbitration logic is included on-chip for
simple, glueless connection of systems containing a maximum of
two SST-Melody-SHARCs and a host processor. Master pro-
cessor changeover incurs only one cycle of overhead. Bus lock
allows indivisible read-modify-write sequences for semaphores.
A vector interrupt is provided for interprocessor commands.
Maximum throughput for interprocessor data transfer is 132 MBytes/s
over the external port.
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S mode (an interface
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